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Content — Intel
®
82575EB Gigabit Ethernet Controller
324632-003 Intel
®
82575EB Gigabit Ethernet Controller
Revision: 2.1 Software Developer’s Manual and EEPROM Guide
January 2011 11
9.0 Ethernet Interface ................................................................................................................ 241
9.1 Internal MAC/PHY 10/100/1000Base-T Interface.......................................................................... 242
9.1.1 MDIO/MDC ........................................................................................................................242
9.2 Duplex Operation for Copper PHY Operation ................................................................................ 243
9.2.1 Full Duplex ........................................................................................................................243
9.2.2 Half Duplex .......................................................................................................................244
9.2.3 Gigabit Physical Coding Sub-Layer (PCS) for SerDes ...............................................................244
9.2.3.1 8B10B Encoding/Decoding ............................................................................................244
9.2.3.2 Code Groups and Ordered Sets ......................................................................................245
9.2.4 SGMII Encoding in 10/100 Mb/s ...........................................................................................245
9.3 Auto-Negotiation and Link Setup ............................................................................................... 246
9.3.1 SerDes Link Configuration ...................................................................................................246
9.3.1.1 SerDes Mode Auto-Negotiation ......................................................................................246
9.3.1.2 PCS Hardware Auto-Negotiation.....................................................................................247
9.3.1.3 Forcing Link ................................................................................................................247
9.3.1.4 Hardware Detection of Non-Auto-Negotiation Partner........................................................248
9.3.1.5 SGMII Auto-Negotiation ................................................................................................248
9.3.2 Copper PHY Link Configuration .............................................................................................249
9.3.2.1 PHY Auto-Negotiation (Speed, Duplex, and Flow Control) ..................................................249
9.3.2.2 MAC Speed Resolution ..................................................................................................249
9.3.2.2.1 Forcing MAC Speed ...................................................................................................249
9.3.2.2.2 Using Internal PHY Direct Link-Speed Indication............................................................250
9.3.2.3 MAC Full/Half Duplex Resolution ....................................................................................250
9.3.2.4 Using PHY Registers .....................................................................................................250
9.3.2.5 Comments Regarding Forcing Link..................................................................................251
9.3.3 Loss of Signal/Link Status Indication.....................................................................................251
9.3.4 Flow Control ......................................................................................................................251
9.3.4.1 MAC Control Frames and Reception of Flow Control Packets ...............................................252
9.3.5 Discard PAUSE Frames and Pass MAC Control Frames .............................................................254
9.3.6 Transmission of PAUSE Frames ............................................................................................254
9.3.7 Software Initiated PAUSE Frame Transmission........................................................................255
9.4 Loopback Support.................................................................................................................... 255
9.4.1 MAC Loopback ...................................................................................................................256
9.4.1.1 Setting the 82575 to MAC Loopback Mode .......................................................................256
9.4.2 Internal PHY Loopback ........................................................................................................256
9.4.2.1 Setting the 82575 to Internal PHY Loopback Mode............................................................256
9.4.3 Internal SerDes Loopback....................................................................................................257
9.4.3.1 Setting Internal SerDes Loopback Mode ..........................................................................257
9.4.4 External PHY Loopback........................................................................................................257
9.4.4.1 Setting External PHY Loopback Mode ..............................................................................258
10.0 802.1q VLAN Support............................................................................................................ 259
10.1 802.1q VLAN Packet Format...................................................................................................... 259
10.1.1 802.1q Tagged Frames .......................................................................................................259
10.2 Transmitting and Receiving 802.1q Packets................................................................................. 260
10.2.1 Adding 802.1q Tags on Transmits.........................................................................................260
10.2.2 Stripping 802.1q Tags on Receives .......................................................................................261
10.3 802.1q VLAN Packet Filtering .................................................................................................... 261
10.4 Double VLAN Support............................................................................................................... 262
11.0 PHY Functionality and Features ............................................................................................ 263
11.1 Auto MDIO Register Initialization ............................................................................................... 263
11.1.1 General Register Initialization ..............................................................................................263
11.1.2 Visible Mirror Bit Initialization...............................................................................................263
11.2 Determining Link State............................................................................................................. 264
11.2.1 False Link..........................................................................................................................264
11.2.2 Forced Operation................................................................................................................265
11.2.3 Auto Negotiation ................................................................................................................265
11.2.4 Parallel Detection ...............................................................................................................266
11.2.5 Auto Cross-Over ................................................................................................................266
11.2.5.1 Support for Different Board Layouts ...............................................................................266