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Intel
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82575EB Gigabit Ethernet Controller — Internal MAC/PHY 10/100/1000Base-T Interface
Intel
®
82575EB Gigabit Ethernet Controller 324632-003
Software Developer’s Manual and EEPROM Guide Revision: 2.1
242 January 2011
The internal copper PHY features 10/100/1000BASE-T signaling and is capable of performing intelligent
power-management based on both the system power-state and LAN energy-detection (detection of
unplugged cables). Power management includes ability to shut-down to extremely low (powered-down)
state when not needed as well as ability to auto-negotiate to lower-speed 10/100 Mb/s operation when
the system is in low power-states.
9.1 Internal MAC/PHY 10/100/1000Base-T
Interface
The 82575 MAC and PHY communicate through an internal 10/100/1000Base-T interface that can be
configured for either 1000 Mb/s operation (GMII) or 10/100 Mb/s (MII) mode of operation. For proper
network operation, both MAC and PHY must be properly configured (either explicitly via software or via
hardware auto-negotiation) to identical speed and duplex settings. All MAC configuration is performed
using device control registers mapped into system memory or I/O space; an internal MDIO/MDC
interface accessible via software is used to configure the PHY operation.
The internal 1000Base-T mode of operation is similar to 10/100Base-T mode of operation. 1000Base-T
mode uses the same MDIO/MDC management interface and registers for PHY configuration as 10/
100Base-T mode. These common elements of operation enable the MAC and PHY to cooperatively
determine link partner's operational capability and configure the hardware based on those capabilities.
• RX_DATA (receive data): Data received by the PHY is transferred to the MAC in 8-bit quantities at
125 MHz in GMII mode.
• RX_ER (receive error): Receive errors are detected by the PHY and signaled to the MAC. Receive
errors may include link coding errors, or any other error detected by the PHY. If receive errors
signaled during packet reception, the MAC can be configured to either receive or drop these
packets.
• RX_DV (receive data valid): This signal is asserted from the PHY to the MAC to transfer valid frame
data to the MAC. It is asserted from the first through the final bytes of a frame, de-asserted after
the final byte. The PHY asserts carriers sense with this data-valid signal de-asserted to indicate to
the MAC reception of broken packet headers (fragments).
9.1.1 MDIO/MDC
The 82575 implements an internal IEEE 802.3 MII Management Interface (also known as the
Management Data Input/Output or MDIO Interface) between the MAC and PHY. This interface provides
the MAC and software the ability to monitor and control the state of the PHY. The internal MDIO
interface defines a physical connection, a special protocol that runs across the connection, and an
internal set of addressable registers. The internal interface consists of a data line (MDIO) and clock line
(MDC), which are accessible by software via the MAC register space.
• MDC (management data clock) — This signal is used by the PHY as a clock timing reference for
information transfer on the MDIO signal. The MDC is not required to be a continuous signal and can
be frozen when no management data is transferred. The MDC signal has a maximum operating
frequency of 2.5 MHz.
• MDIO (management data I/O) — This internal signaling between the MAC and PHY logically
represents a bi-directional data signal used to transfer control information and status to and from
the PHY (to read and write the PHY management registers). Asserting and interpreting value(s) on
this interface requires knowledge of the special MDIO protocol to avoid possible internal signal
contention or miscommunication to/from the PHY.