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Interrupt Cause Set Register - ICS (000C8h; WO) — Intel
®
82575EB Gigabit Ethernet Controller
324632-003 Intel
®
82575EB Gigabit Ethernet Controller
Revision: 2.1 Software Developer’s Manual and EEPROM Guide
January 2011 341
14.3.35 Interrupt Cause Set Register - ICS (000C8h;
WO)
Software uses this register to set an interrupt condition. Any bit written with a 1b sets the
corresponding interrupt. This results in the corresponding bit being set in the Interrupt Cause Read
Register (see Section 14.3.34). A PCIe* interrupt is generated if one of the bits in this register is set
and the corresponding interrupt is enabled through the Interrupt Mask Set/Read Register (see
Section 14.3.36).
Bits written with 0 are unchanged.
GPI_SDP2 13 0b General Purpose Interrupt on SDP2
If GPI interrupt detection is enabled on this pin (via CTRL_EXT), this interrupt cause is
set when the SDP2 is sampled high.
GPI_SDP3 14 0b General Purpose Interrupt on SDP3
If GPI interrupt detection is enabled on this pin (via CTRL_EXT), this interrupt cause is
set when the SDP3 is sampled high.
Reserved 17:15 000b Reserved
MNG 18 0b Manageability Event Detected
Indicates that a manageability event happened. When the 82575 is at power down
mode, the IPMI can generate a PME for the same events that would cause an interrupt
when the 82575 is at the D0 state.
Reserved 19 0b Reserved
OMED 20 0b Other Media Energy Detect
When in SerDes/SGMII mode, indicates that link status has changed on the 1000BASE-T
PHY or when in 1000BASE-T PHY mode, there is a change in SerDes/SGMII link status.
Reserved 21 0b Reserved
RX PBUR 22 0b Rx Packet Buffer Unrecoverable Error
This bit is set when an unrecoverable error is detected in the packet buffer memory for a
Rx packet.
TX PBUR 23 0b Tx Packet Buffer Unrecoverable Error
This bit is set when an unrecoverable error is detected in the packet buffer memory for a
Tx packet.
RX DHER 24 0b Rx Descriptor Handler Error
This bit is set when an unrecoverable error is detected in the descriptor handler memory
for Rx descriptors.
TX DHER 25 0b Tx Descriptor Handler Error
This bit is set when an unrecoverable error is detected in the descriptor handler memory
for Tx descriptors.
SW WD 26 0b SW Watchdog
This bit is set after a software watchdog timer times out.
Reserved 27 0b Reserved
OUTSYNC 28 0b DMA Tx Detected out of Sync Situation
Occurs when the amount of data in DMA is not equal to the amount of data pointed to by
the descriptor.
Note: This bit should never get set during normal operation.
Reserved 31:29 0000b Reserved
Field Bit(s)
Initial
Value
Description