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PHY Functionality and Features — Intel
®
82575EB Gigabit Ethernet Controller
324632-003 Intel
®
82575EB Gigabit Ethernet Controller
Revision: 2.1 Software Developer’s Manual and EEPROM Guide
January 2011 263
11.0 PHY Functionality and Features
The PHY default configuration is determined by data from the EEPROM, read right after power-on reset.
11.1 Auto MDIO Register Initialization
The 82575 PHYs support an option for automatically initializing MDIO registers with values from
EEPROM/ROM, in case defaults in hardware are not adequate. In the 82575, this is performed by
firmware.
There are two types of register initialization:
1. General register initialization - any register in a PHY can be initialized.
2. Customer visible mirror bit initialization - there are some bits in PHY that are a mirror of a customer
visible EEPROM bits (PHY register 25 bits 3:0 and 6 and PHY register 26 bit 0).
After any PHY reset (power down included), a PHY needs to be initialized.
The register initialization is done by the firmware through the MAC/PHY MDIO interface (MDIC).
11.1.1 General Register Initialization
A block of data is allocated in EEPROM/ROM. This block holds register addresses and data in MDIC
format.
Each time a PHY reset ends, this block is read from EEPROM /ROM (first from ROM then from EEPROM)
by firmware and is written to the PHY registers through the MDIC register and MDIO interface.
11.1.2 Visible Mirror Bit Initialization
There are a number of visible bits that reside in the EEPROM/MAC control registers that have a mirror
bit in the PHY registers. These bits are also updated by firmware after every PHY reset.
These bits are updated after the General Register initialization and through a read modify write
sequence.
The current visible mirror bits are in PHY register 25 (bits 3:0 and bit 6) and PHY register 26 (bit 0).
The PHY might perform some low level initialization such as DSP configuration based on EEPROM
settings. The details of those initialization are beyond the scope of this Software Developers Manual.