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82575EB Gigabit Ethernet Controller — Content
Intel
®
82575EB Gigabit Ethernet Controller 324632-003
Software Developer’s Manual and EEPROM Guide Revision: 2.1
12 January 2011
11.3 Link Criteria............................................................................................................................ 267
11.3.1 1000BASE-T ..................................................................................................................... 267
11.3.2 100BASE-TX..................................................................................................................... 267
11.3.3 10BASE-T......................................................................................................................... 267
11.4 Link Enhancements.................................................................................................................. 267
11.4.1 SmartSpeed ..................................................................................................................... 267
11.4.1.1 Using SmartSpeed .......................................................................................................268
11.4.2 Flow Control ..................................................................................................................... 268
11.5 Management Data Interface...................................................................................................... 269
11.6 Low Power Operation ............................................................................................................... 269
11.7 Power Down via the PHY Register .............................................................................................. 269
11.8 1000 Mb/s Operation ............................................................................................................... 269
11.8.1 Transmit Functions ............................................................................................................ 270
11.8.1.1 Scrambler ...................................................................................................................270
11.8.2 Transmit FIFO................................................................................................................... 271
11.8.2.1 Transmit Phase-Locked Loop PLL....................................................................................271
11.8.2.2 Trellis Encoder.............................................................................................................271
11.8.2.3 4DPAM5 Encoder..........................................................................................................271
11.8.2.4 Spectral Shaper ...........................................................................................................271
11.8.2.5 Low-Pass Filter ............................................................................................................272
11.8.2.6 Line Driver ..................................................................................................................272
11.8.2.7 Transmit/Receive Flow..................................................................................................272
11.8.3 Receive Functions.............................................................................................................. 273
11.8.3.1 Hybrid ........................................................................................................................273
11.8.3.2 Automatic Gain Control .................................................................................................273
11.8.3.3 Timing Recovery ..........................................................................................................273
11.8.3.4 Analog-to-Digital Converter ...........................................................................................273
11.8.3.5 Digital Signal Processor.................................................................................................273
11.8.3.6 Descrambler................................................................................................................273
11.8.3.7 Viterbi Decoder/Decision Feedback Equalizer (DFE)...........................................................274
11.8.3.8 4DPAM5 Decoder .........................................................................................................274
11.9 100 Mb/s Operation ................................................................................................................. 274
11.10 10 Mb/s Operation................................................................................................................... 274
11.10.1 Link Test.......................................................................................................................... 274
11.10.2 10Base-T Link Failure Criteria and Override .......................................................................... 275
11.10.3 Jabber ............................................................................................................................. 275
11.10.4 Polarity Correction............................................................................................................. 275
11.10.5 Dribble Bits ...................................................................................................................... 275
12.0 Configurable LED Outputs ..................................................................................................... 277
13.0 Dual Port Characteristics ...................................................................................................... 279
13.1 Features of Each MAC .............................................................................................................. 279
13.1.1 PCIe* Interface................................................................................................................. 279
13.1.2 MAC Configuration Register Space ....................................................................................... 281
13.1.3 SDP, LED, INT# Output...................................................................................................... 281
13.2 Shared EEPROM ...................................................................................................................... 281
13.3 Shared FLASH ......................................................................................................................... 281
13.3.1 FLASH Access Contention ................................................................................................... 281
13.4 Link Mode/Configuration........................................................................................................... 282
13.5 LAN Disable ............................................................................................................................ 282
13.5.1 Overview ......................................................................................................................... 282
13.5.2 Multi-Function Advertisement.............................................................................................. 283
13.5.3 Legacy Interrupt Use ......................................................................................................... 283
13.5.4 Power Reporting................................................................................................................ 283
13.6 Device Disable ........................................................................................................................ 283
13.6.1 BIOS Handling of Device Disable ......................................................................................... 284
13.7 Copper/Fiber Switch................................................................................................................. 284
14.0 Register Descriptions............................................................................................................ 287
14.1 Register Conventions ............................................................................................................... 287