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82575EB Gigabit Ethernet Controller — Transmit Descriptor Control - TXDCTL (03828h +
100*n [n=0..3]; R/W)
Intel
®
82575EB Gigabit Ethernet Controller 324632-003
Software Developer’s Manual and EEPROM Guide Revision: 2.1
368 January 2011
• Queue1 - TDT1 (03918h)
• Queue2 - TDT2 (03A18h)
• Queue3 - TDT3 (03B18h)
14.3.73 Transmit Descriptor Control - TXDCTL (03828h
+ 100*n [n=0..3]; R/W)
These registers control the fetching and write-back of transmit descriptors. The three threshold values
are used to determine when descriptors are read from and written to host memory. The values are in
units of descriptors (each descriptor is 16 bytes).
Since write-back of transmit descriptors is optional (under the control of RS bit in the descriptor), not
all processed descriptors are counted with respect to WTHRESH. Descriptors start accumulating after a
descriptor when RS is set. In addition, with transmit descriptor bursting enabled, some descriptors are
written back that did not have RS set in their respective descriptors.
Note: When WTHRESH = 0b, only descriptors with the RS bit set are written back
• Queue0 - TXDCTL0 (03828h)
• Queue1 - TXDCTL1 (03928h)
• Queue2 - TXDCTL2 (03A28h)
• Queue3 - TXDCTL3 (03B28h)
Field Bit(s)
Initial
Value
Description
TDT 15:0 00h Transmit Descriptor Tail
Reserved 31:16 00h Reserved
Reads as 0b.
Should be written to 00h for future compatibility.
Field Bit(s)
Initial
Value
Description
PTHRESH 5:0 00h Prefetch Threshold
Controls when a prefetch of descriptors is considered. This threshold refers to the
number of valid, unprocessed transmit descriptors the 82575 has in its on-chip buffer.
If this number drops below PTHRESH, the algorithm considers pre-fetching descriptors
from host memory. However, this fetch does not happen unless there are at least
HTHRESH valid descriptors in host memory to fetch.
Note: HTHRESH should be given a non zero value each time PTHRESH is used.
Reserved 7:6 00h Reserved
HTHRESH 13:8 00h Host Threshold
Reserved 15:14 00h Reserved
Reads as 0b. Should be written as 0b for future compatibility.
WTHRESH 21:16 00h Write-Back Threshold
Controls the write-back of processed transmit descriptors. This threshold refers to the
number of transmit descriptors in the on-chip buffer that are ready to be written back
to host memory. In the absence of external events (explicit flushes), the write-back
occurs only after at least WTHRESH descriptors are available for write-back.
Note: Since the default value for write-back threshold is 0b, descriptors are normally
written back as soon as they are processed. WTHRESH must be written to a non-zero
value to take advantage of the write-back bursting capabilities of the 82575.