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Internal SerDes Loopback — Intel
®
82575EB Gigabit Ethernet Controller
324632-003 Intel
®
82575EB Gigabit Ethernet Controller
Revision: 2.1 Software Developer’s Manual and EEPROM Guide
January 2011 257
— Clear the Loopback bit (bit 14)
— Set the Auto Neg Enable bit (bit 12)
— Register values should be:
a. For 10 Mb/s 4100h.
b. For 100 Mb/s 6100h.
c. For 1000 Mb/s 4140h.
d. In the Port Control register, address 16 (10h) in the PHY, set bit 14 (Link Disable). This is not
required for 1 Gb/s but required for 10/100 Mb/s.
9.4.3 Internal SerDes Loopback
In internal SerDes loopback, the PHY block is not functional and data is looped back at the end of the
SerDes functionality. This means that the only design that is functional in SerDes/SGMII mode is
involved in the loopback.
9.4.3.1 Setting Internal SerDes Loopback Mode
The following procedure should be used to put the 82575 in SerDes loopback mode:
• Set link mode to SerDes: CTRL_EXT.LINK_MODE (CSR 18h, bits 23:22) = 11b
• Configure the SerDes (register 4, bit 1) to loopback: write to SERDESCTL (CSR 00024h) the value
410h
• Move to force mode by setting the following bits:
— CTRL.FD (CSR 0h, bit 0) = 1b
— CTRL.SLU (CSR 0h, bit 6) = 1b
— CTRL.RFCE (CSR 0h, bit 27) = 0b
— CTRL.TFCE (CSR 0h, bit 28) = 0b
— CTRL.LRST (CSR 0h, bit 3) = 0b
— PCS_LCTL.FORCE_LINK (CSR 04208h, bit 5) = 1b
— PCS_LCTL.FSD (CSR 04208h, bit 4) = 1b
— PCS_LCTL.FDV (CSR 04208h, bit 3) = 1b
— PCS_LCTL.FLV (CSR 04208h, bit 0) = 1b
— PCS_LCTL.AN_ENABLE (CSR 04208h, bit 16) = 0b
— CONNSW.ENRGSRC (CSR 00034h, bit 2) = 0b
9.4.4 External PHY Loopback
In external PHY loopback, the SerDes block is not functional and data is sent through the MDI interface
and looped back using an external loopback plug. This means that the only design that is functional in
copper mode is involved in the loopback. If connected at 10/100 Mb/s, the loopback operates without
any special setup.