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SerDes Link Configuration — Intel
®
82575EB Gigabit Ethernet Controller
324632-003 Intel
®
82575EB Gigabit Ethernet Controller
Revision: 2.1 Software Developer’s Manual and EEPROM Guide
January 2011 247
A set of registers is provided to facilitate hardware Auto-Negotiation.
Note: Hardware Auto-Negotiation can be initiated at power up or assertion of GIO_PWR_GOOD by
enabling specific bits in the EEPROM.
9.3.1.2 PCS Hardware Auto-Negotiation
Hardware supports negotiation of the link configuration per clause 37 of the 802.3z standard. This is
accomplished by the exchange of /C/ ordered sets that contain the capabilities defined in the
PCS_ANADV register in the 3rd and 4th symbols of the ordered sets. Next page are supported using the
PCS_NPTX_AN register.
Bits FD and LU of the Device Status register (STATUS), and bits in the PCS_LSTS register provide status
information regarding the negotiated link.
Auto-Negotiation can be initiated by the following:
• LRST transition from 1b to 0b
• PCS_LCMD.AN_ENABLE transition from 0b to 1b
• Receipt of /C/ ordered set during normal operation
• Receipt of different value of the /C/ ordered set during the negotiation process
• Transition from loss of synchronization to synchronized state (if AN_ENABLE is set).
• PCS_LCMD.AN_RESTART transition from 0b to 1b
Resolution of the negotiated link determines 82575 operation with respect to flow control capability and
duplex settings. These negotiated capabilities override advertised and software controlled 82575
configuration.
Software must configure the PCS_ANADV fields to the desired advertised base page. The bits in the
Device Control register are not mapped to the txConfigWord field in hardware until after Auto-
Negotiation completes. The figures that follow show the mapping of the PCS_ANADV fields to the
Config_reg Base Page encoding per clause 37 of the standard.
Figure 26. 802.3z Advertised Base Page Mapping
The partner advertisement can be seen in the PCS_ LPAB and PCS_ LPABNP registers.
9.3.1.3 Forcing Link
Forcing link can be accomplished by software writing a 1b to CTRL.SLU which forces the MAC PCS logic
into a link up state (enables listening to incoming characters when LOS is de-asserted by the internal or
external SerDes).
Note: The PCS_LCMD.AN_ENABLE bit must be set to logic 0b to enable for forcing link.
When link is forced via the CTRL.SLU bit, the link does not come up unless the LOS signal is
de-asserted or an energy indication is received from the SerDes receiver, implying that
15 14 13:12 11:9 8:7 6 5 4:0
Nextp ACK RFLT Rsv ASM HD FD Rsv
15 14 13:12 11:9 8:7 6 5 4:0
Nextp ACK RFLT Rsv ASM HD FD Rsv