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Intel
®
82575EB Gigabit Ethernet Controller — MAC Loopback
Intel
®
82575EB Gigabit Ethernet Controller 324632-003
Software Developer’s Manual and EEPROM Guide Revision: 2.1
256 January 2011
Figure 28. 82575 Loopback Modes
9.4.1 MAC Loopback
In MAC loopback, the PHY and SerDes blocks are not functional and data is looped back before these
blocks. MAC loopback is operational only when operating in PHY mode (CTRL_EXT.LINK_MODE = 00b).
9.4.1.1 Setting the 82575 to MAC Loopback Mode
The following procedure should be used to place the 82575 in MAC loopback mode:
• Set RCTL.LBM to 01b (bits 7:6)
• Set CTRL.SLU (bit 6; should be set by default)
• Set CTRL.FRCSPD and FRCDPLX (bits 11 and 12)
• Set CTRL.SPEED to 10b (1 Gb/s) and CTRL.FD
• Set CTRL.ILOS.
Filter configuration and other TX/RX processes are as the same as I n normal mode.
Note: This configuration can be used when there is no link in the PHY. If there is a link then the
ILOS bit should be cleared.
9.4.2 Internal PHY Loopback
In internal PHY loopback, the SerDes block is not functional and data is looped back at the end of the
PHY functionality. This means that the only design that is functional in copper mode is involved in the
loopback.
9.4.2.1 Setting the 82575 to Internal PHY Loopback Mode
The following procedure should be used to put the 82575 in internal PHY loopback mode:
• Set Link mode to PHY: CTRL_EXT.LINK_MODE (CSR 18h, bits 23:22) = 00b
• In the PHY control register (address 0 in the PHY):
— Set duplex mode (bit 8)
MAC
Packet Buffer
and DMA
SerDes
Interface
Internal
PHY
GMII
PCIe
SerDes
SGMII
1GbT
2
3
4
1