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Write to Clear — Intel
®
82575EB Gigabit Ethernet Controller
324632-003 Intel
®
82575EB Gigabit Ethernet Controller
Revision: 2.1 Software Developer’s Manual and EEPROM Guide
January 2011 169
5.15.2 Write to Clear
In the case where the software device driver wants to configure itself in MSI-X mode to not use the
auto-clear feature, it might clear the EICR bits by writing to the EICR register. Any bits written with a 1b
is cleared. Any bits written with a 0b remain unchanged.
5.15.3 Read to Clear
The EICR and ICR registers are cleared on a read.
Note: The software device driver should never do a read-to-clear of the EICR when in MSI-X
mode, since this can clear interrupt cause events which are processed by a different
interrupt handler (assuming multiple vectors).
5.16 Dynamic Interrupt Moderation
There are some types of network traffic for which latency is a critical issue. For these types of traffic,
interrupt moderation hurts performance by increasing latency between when a packet is received by
hardware and when it is indicated to the host operating system. This traffic can be identified by the TCP
port value in conjunction with control bits, size and VLAN priority.
The 82575 implements an eight-entry, software programmable, table of TCP ports and eight registers
with control bits filter and size threshold. In addition, a dedicated register enables setting of a VLAN
priority threshold. If a packet is received on one of these TCP ports, and the conditions set by the
register fit to the packet, hardware should interrupt immediately, overriding the interrupt moderation
by the EITR counter.
A Port Enabling bit allows enabling or disabling of a specific port for this purpose; VLAN priority filtering
allows issuing of immediate interrupt.
The logic of the dynamic interrupt moderation is as follows:
• There are eight port filters. Each filter checks the value of incoming packets TCP port, size, and
control bits against values stored in the filter's register. Each parameter can be bypassed (or via a
wildcard). Each filter can be enabled or disabled. If one of the filters detects an adequate packet, an
immediate interrupt is issued.
• When VLAN priority filtering is enabled, VLAN packets trigger an immediate interrupt when the
VLAN priority is equal to or above the VLAN priority threshold. This is regardless of the status of the
port filters.
Note: EITR is reset to 0b following a dynamic interrupt.
Immediate interrupts are available only when using advanced receive descriptors as
opposed to legacy descriptors.