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Intel
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82575EB Gigabit Ethernet Controller — Packet Generator StaPGSTS Bit Description
Intel
®
82575EB Gigabit Ethernet Controller 324632-003
Software Developer’s Manual and EEPROM Guide Revision: 2.1
444 January 2011
14.11.8 Packet Generator StaPGSTS Bit Description
14.11.9 Packet Generator ContPGCTL Bit Description
Field Bit(s)
Initial
Value
Description
Fail Data 0 0b Fail Data
The data received is different than the data expected.
Fail Header 1 0b Fail Header
The header received is different than the header expected (DA and SA).
Fail Length 2 0b Fail Header
The length field received is different than the length field expected.
Receive Done 3 0b Receive Done
Receive process done. Cleared when PGNP.Start is set.
Transmit Done 4 0b Transmit Done
Transmit process done. Cleared when PGNP.Start is set.
Reserved 15:5 0h Reserved
NRCVPK 31:16 0h Number of Received Packets
Field Bit(s)
Initial
Value
Description
PG Mode 0 0b Packet Generator Mode
When set, the source of packets sent to the network is the packet generator. When
cleared, the packets from the host or manageability are used to feed the MAC.
Add CRC 1 1b Add CRC
1b = Added by MAC.
0b = No CRC added.
Destination 3:2 00b Destination of Packets
00b = Send To MAC.
01b = Reserved.
10b = Send to MAC and MNG.
10b = Send to MNG.
Length 4 0b Length Mode
Defines the algorithm used to determine the packet length.
0b = Incremental.
1b = Use LFSR output.