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82575EB Gigabit Ethernet Controller — Legacy Receive Descriptor Format
Intel
®
82575EB Gigabit Ethernet Controller 324632-003
Software Developer’s Manual and EEPROM Guide Revision: 2.1
108 January 2011
Table 29. Receive Errors (RDESC.ERRORS) Layout
The IP and TCP checksum error bits are valid only when the IPv4 or TCP/UDP checksum(s) is performed
on the received packet as indicated via IPCS and TCPCS. These, along with the other error bits are valid
only when the EOP and DD bits are set in the descriptor.
Note: Receive checksum errors have no affect on packet filtering.
7 6 5 4 3 2 1 0
RXE IPE TCPE CXE LE SEQ SE CE
Field Bit(s) Description
RXE 7 Rx Data Error.
Indicates that a data error occurred during the packet reception. A data error refers to the
reception of a /FE/ code from the XGMII interface which eventually causes a CRC error
detection (CE bit). This bit is valid only when the EOP and DD bits are set and is not set in
descriptors unless RCTL.SBP is set. The RXE bit can also be set if a parity error was
discovered in the packet buffer while reading this packet. In this case, RXE might be set
even if RCTL.SBP is not set.
IPE 6 IPv4 Checksum Error.
Indicates that the IPv4 header checksum is incorrect. If IPv4 checksum offload is disabled
by RXCSUM.IPOFL, this bit is 0b.
TCPE 5 TCP/UDP Checksum Error.
Indicates that the TCP or UDP checksum is incorrect. If TCP/UDP checksum offload is
disabled by RXCSUM.TUOFL, this bit is 0b.
The IP and TCP checksum error bits are valid only when the IPv4 or TCP/UDP checksum(s) is
performed on the received packet as indicated via IPCS and TCPCS. These, along with the
other error bits, are valid only when the EOP and DD bits are set in the descriptor.
Note: Receive checksum errors have no effect on packet filtering.
If receive checksum offloading is disabled (RXCSUM.IPOFL & RXCSUM.TUOFL), then the IPE
and TCPE bits are 0b.
In 10/100/1000BASE-T mode, the RXE bit indicates that a data error occurred during the
packet reception that has been detected by the PHY. This generally corresponds to signal
errors occurring during the packet reception. This bit is valid only when the EOP and DD bits
are set and is not set in descriptors unless RCTL.SBP is set.
CRC errors and alignment errors are both indicated via the CE bit. Software might
distinguish between these errors by monitoring the respective statistics registers.
CXE 4 Carrier Extension Error
Reads as 0b.
LE 3 Length Error
Indicates packets with length error. For example, indicates valid packets (no CRC error) with
a type/length field with a value lower or equal 1500 greater than the L2 payload size.
Packets with length error are forwarded to the host only if the RFCTL.LEF bit is set or
RFCTL.SBP bit is set.
SEQ 2 Sequence Error
In 802.3 implementations, this would be classified as a framing error.
A valid delimiter sequence consists of:
idle start-of-frame (SOF) data, pad (optional) end-of-frame (EOF) fill (optional)
idle.
SE 1 Symbol Error.
CE 0 CRC Error or Alignment Error.
Indicates an Ethernet CRC error was detected. This bit is valid only when the EOP and DD
bits are set and is not set in descriptors unless RCTL.SBP is set.