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Loss of Signal/Link Status Indication — Intel
®
82575EB Gigabit Ethernet Controller
324632-003 Intel
®
82575EB Gigabit Ethernet Controller
Revision: 2.1 Software Developer’s Manual and EEPROM Guide
January 2011 251
• Resetting the PHY
• Setting preferred link configuration for advertisement during the Auto-Negotiation process
• Restarting the Auto-Negotiation process
• Reading Auto-Negotiation status from the PHY
• Forcing the PHY to a specific link configuration
9.3.2.5 Comments Regarding Forcing Link
Forcing link in internal PHY mode requires the software driver to configure both the MAC and the PHY in
a consistent manner with respect to each other as well as the link partner. After initialization, the
software driver configures the desired modes in the MAC, then accesses the PHY MII registers to set the
PHY to the same configuration.
Before enabling the link, the speed and duplex settings of the MAC can be forced by software using the
CTRL.FRCSPD, CTRL.FRCDPX, CTRL.SPEED, and CTRL.FD bits. After the PHY and MAC have both been
configured, the software device driver should write a 1b to the CTRL.SLU bit.
9.3.3 Loss of Signal/Link Status Indication
For either internal PHY, SerDes or SGMII modes of operation, an LOS/LINK signal provides an indication
of physical link status to the MAC. When the MAC is configured for Optical SerDes mode, the input
reflects loss-of-signal connection from the optics. In backplane mode, where there is no LOS external
indication, an internal indication from the SerDes receiver can be used. In SFP systems the LOS
indication from the SFP can be used. In internal PHY mode, this signal from the PHY indicates whether
the link is up or down; typically indicated after successful Auto-Negotiation. Assuming that the MAC has
been configured with CTRL.SLU = 1b, the MAC status bit STATUS.LU, when read generally reflects
whether the PHY or SerDes has link (except under forced-link setup where even the PHY link indication
may have been forced).
When the link indication from the PHY is de-asserted (or the loss-of-signal asserted from the SerDes),
the MAC considers this to be a transition to a link-down situation (for example, cable unplugged, loss of
link partner, etc.). If the Link Status Change (LSC) interrupt is enabled, the MAC generates an interrupt
to be serviced by the software device driver.
9.3.4 Flow Control
Flow control as defined in IEEE specification 802.3x, as well as the specific operation of asymmetrical
flow control defined by 802.3z, are supported. The following registers are defined for the
implementation of flow control:
Table 80. Flow Control Registers
Register Name Description
CTRL.RFCE Enables the reception of legacy flow control packets
CTRL.TFCE Enables the transmission of legacy flow control packets
Flow Control Address Low, High (FCAL/H) 6-byte flow control multicast address
Flow Control Type (FCT) 16-bit field to indicate flow control type
Flow Control Receive Thresh Hi (FCRTH) 13-bit high water mark indicating receive buffer fullness