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Intel
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82575EB Gigabit Ethernet Controller — PCIe* Interface
Intel
®
82575EB Gigabit Ethernet Controller 324632-003
Software Developer’s Manual and EEPROM Guide Revision: 2.1
280 January 2011
Many of the fields of the PCIe* header space contain hardware default values that are either fixed or
can be overridden using EEPROM, but cannot be independently specified for each logical LAN device.
The following fields are considered to be common to both LAN devices:
The following fields are implemented unique to each LAN device:
28h Cardbus CIS Pointer (not used)
2Ch Subsystem ID Subsystem Vendor ID
30h Expansion ROM Base Address
34h Reserved Cap_Ptr
38h Reserved
3Ch Max_Latency 00h Min_Grant
FFh
Interrupt Pin
01h or 02h)
Interrupt Line
00h
Vendor ID Vendor ID is fixed to 8086 and is not readable from EEPROM.
Revision The revision number of the 82575 is reflected identically for both LAN devices.
Header Type This field indicates if a device is single function or multifunction. The value reflected in this field is
reflected identically for both LAN devices, but the actual value reflected depends on LAN Disable
configuration.
When both 82575 LAN ports are enabled, both PCI headers return 80h in this field, acknowledging
being part of a multi-function device. LAN A exists as device “function 0”, while LAN B exists as
device “function 1”.
If one of the LAN ports is disabled, then only a single-function device is indicated (this field returns
a value of 00h), and the LAN exists as device “function 0”.
Subsystem ID The Subsystem ID of the 82575 can be specified via EEPROM, but only a single value can be
specified. The value is reflected identically for both LAN devices.
Subsystem Vendor ID The Subsystem Vendor ID of the 82575 can be specified via EEPROM, but only a single value can
be specified. The value is reflected identically for both LAN devices.
Class Code,
Cap_Ptr,
Max Latency,
Min Grant
These fields reflect fixed values that are constant values reflected for both LAN devices.
Device ID The Device ID reflected for each LAN device can be independently specified via EEPROM.
Command,
Status
Each LAN device implements its own command/status registers.
Latency Timer,
Cache Line Size
Each LAN device implements these registers uniquely. The system should program these fields
identically for each LAN to ensure consistent behavior and performance of each device.
Memory BAR,
Flash BAR,
IO BAR,
Expansion ROM BAR
Each LAN device implements its own Base Address registers, allowing each device to claim its own
address region(s).
Interrupt Pin Each LAN device independently indicates which interrupt pin (INTA# or INTB#) is used by that
82575’s MAC to signal system interrupts. The value for each LAN device can be independently
specified via EEPROM, but only if both LAN devices are enabled.
Byte Offset Byte 0 Byte 1 Byte 2 Byte 3