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Intel
®
82575EB Gigabit Ethernet Controller — Packet Buffer Memory - PBM (10000h - 10FFCh; R/
W)
Intel
®
82575EB Gigabit Ethernet Controller 324632-003
Software Developer’s Manual and EEPROM Guide Revision: 2.1
438 January 2011
14.10.16 Packet Buffer Memory - PBM (10000h - 10FFCh;
R/W)
All PBM (FIFO) data is available to diagnostics. Locations can be accessed as 32-bit or 64-bit words.
The packet buffer line is 128 bits. In order to write to the packet buffer programmers should write four
times in a row (for example, to addresses 10000h, 10004h, 10008h, and 1000Ch). Only after writing
the last address can data be loaded and the new value read.
The internal PBM is 48 KB in size. Software can configure the amount of PBM space that is used as the
transmit FIFO versus the receive FIFO. The default is 14 KB of transmit FIFO space and 34 KB of receive
FIFO space. Regardless of the individual FIFO sizes that software configures, the Rx FIFO is located first
in the memory mapped PBM space. For the default FIFO configuration, the Rx FIFO occupies the first 34
KB of the packet buffer while the Tx FIFO occupies the last
14 KB of the packet buffer.
Note: The packet buffer is accessible by pages of 4 KB. This accessed page is set in the PBMPN
register.
14.10.17 Packet Buffer Memory Page NPBMPN Register
Bit Description
14.10.18 Rx Descriptor Handler Memory Page Number -
RDHMP (025FCh; R/W)
Field Bit(s)
Initial
Value
Description
FIFO Data 31:0 X Packet Buffer Data
Field Bit(s)
Initial
Value
Description
Page 5:0 0h Packet Buffer Accessed Page (4 KB)
Allowed values for the 82575 are 00h:0Bh
Reserved 31:6 0h Reserved
Field Bit(s)
Initial
Value
Description
Page 3:0 0h Rx Descriptor Handler Accessed Page (4KB)
Only allowed value for the 82575 is zero.
Reserved 27:4 0h Reserved