Filter
Top Products
Intel
®
82575EB Gigabit Ethernet Controller — Flash Access Contention
Intel
®
82575EB Gigabit Ethernet Controller 324632-003
Software Developer’s Manual and EEPROM Guide Revision: 2.1
52 January 2011
4.4.1 Flash Access Contention
The 82575 implements internal arbitration between Flash accesses initiated through the LAN 0 device
and those initiated through the LAN 1 device. If accesses from both LAN devices are initiated during the
same approximate size window, the first one is served first and only then the next one. Note that the
82575 does not synchronize between the two entities accessing the Flash though contentions caused
from one entity reading and the other modifying the same locations is possible.
To avoid this contention, accesses from both LAN devices should be synchronized using external
software synchronization of the memory or I/O transactions responsible for the access. It might be
possible to ensure contention-avoidance simply by nature of software sequence.
4.4.2 Flash Deadlock Avoidance
The flash is a shared resource between the following clients:
• Accesses of port 0 LAN driver
• Accesses of port 1 LAN driver
• BIOS Parallel access via expansion ROM mechanism
• Firmware accesses
All clients can access the EEPROM using parallel access, where hardware implements the actual access
to the flash. Hardware can schedule these accesses so that all the clients get served without starvation.
However, software and hardware clients can access the serial flash using bit banging. In this case, there
is a request/grant mechanism that locks the serial flash to the exclusive usage of one client. If this
client is stuck without releasing the lock, the other clients cannot access the flash. In order to avoid
this, the 82575 implements a timeout mechanism, which releases the grant from a client that did not
toggle the flash bit-bang interface for more than two seconds.
Consequently, if an agent that was granted access to the flash for bit-bang access did not toggle the
bit-bang interface for 500 ms, it should check if it still owns the interface before continuing bit banging.
This mode is enabled by bit 5 in word 0Ah of the EEPROM.
4.5 EEPROM Map
Table 4 lists the EEPROM map for the 82575.
Table 4. 82575 EEPROM Map
Word
Used
By
1
High Byte (15:8) Low Byte (7:0)
Image
Value
LAN 0/1
00h HW Ethernet Address Byte 2 Ethernet Address Byte 1 IA(2,1) Both
01h HW Ethernet Address Byte 4 Ethernet Address Byte 3 IA(4,3) Both
02h HW Ethernet Address Byte 6 Ethernet Address Byte 5 IA(6,5) Both
03h:
07h
SW Compatibility (High Byte) Compatibility (Low Byte) 0000h Both
08h SW PBA Byte 1 PBA Byte 2