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Intel
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82575EB Gigabit Ethernet Controller — Extended Interrupt Cause Set Register (EICS)
Intel
®
82575EB Gigabit Ethernet Controller 324632-003
Software Developer’s Manual and EEPROM Guide Revision: 2.1
164 January 2011
5.13.7 Extended Interrupt Cause Set Register (EICS)
This registers enables the setting of bits in EICR, by software, by writing a 1b in the corresponding bits
in EICS. Used to rearm interrupts software did not have time to handle in the current interrupt routine.
5.13.8 Extended Interrupt Mask Set and Read Register
(EIMS)/Extended Interrupt Mask Clear Register
(EIMC)
Interrupts appear on PCIe* only if the interrupt cause bit is set to 1b and the corresponding interrupt
mask bit is set to 1b. Software blocks asserting an interrupt by clearing the corresponding bit in the
mask register. The cause bit stores the interrupt event regardless of the state of the mask bit. Clear and
set make this register more thread safe by avoiding a read-modify-write operation on the mask
register. The mask bit is set for each bit written to a one in the set register and cleared for each bit
written in the clear register. Reading the set register (EIMS) returns the current mask register value.
5.13.9 Extended Interrupt Auto Clear Enable Register
(EIAC)
Each bit in this register enables clearing of the corresponding bit in EICR following interrupt generation.
When a bit is set, the corresponding bit in EICR is automatically cleared following an interrupt. This
feature should only be used in MSI-X mode.
When used in conjunction with MSI-X interrupt vector, this feature enables interrupt cause recognition
and selective interrupt cause without requiring software to read or write the EICR register; therefore,
the penalty related to a PCIe* read or write transaction is avoided (Section 5.15).
5.13.10 Extended Interrupt Auto Mask Enable Register
(EIAM)
Each bit set in this register enables clearing of the corresponding bit in EIMS following read or write-to-
clear to EICR. It also enables setting of the corresponding bit in EIMS following a write-to-set to EICS.
This mode is provided in case MSI-X is not used. As a result, auto-clear through EIAC register is not
available.
In MSI-X mode, the software device driver might set the bits of this register to select mask bits that are
reset during interrupt processing. In this mode, each bit in this register enables clearing of the
corresponding bit in EIMC following interrupt generation.