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Content — Intel
®
82575EB Gigabit Ethernet Controller
324632-003 Intel
®
82575EB Gigabit Ethernet Controller
Revision: 2.1 Software Developer’s Manual and EEPROM Guide
January 2011 5
4.2 Flash Interface Operation ........................................................................................................... 49
4.2.1 Flash Write Control.............................................................................................................. 50
4.2.2 Flash Erase Control.............................................................................................................. 50
4.3 Shared EEPROM ........................................................................................................................ 50
4.3.1 EEPROM Deadlock Avoidance ................................................................................................ 50
4.3.2 EEPROM Map Shared Words.................................................................................................. 51
4.4 Shared FLASH........................................................................................................................... 51
4.4.1 Flash Access Contention ....................................................................................................... 52
4.4.2 Flash Deadlock Avoidance..................................................................................................... 52
4.5 EEPROM Map ............................................................................................................................ 52
4.5.1 Hardware Accessed Words....................................................................................................54
4.5.1.1 Ethernet Address (Words 00h – 02h) ............................................................................... 56
4.5.1.2 Initialization Control 1 (Word 0Ah) .................................................................................. 56
4.5.1.3 Subsystem ID (Word 0Bh) ............................................................................................. 57
4.5.1.4 Subsystem Vendor ID (Word 0Ch)................................................................................... 57
4.5.1.5 Device ID (Word 0Dh, 11h) ............................................................................................ 57
4.5.1.6 Dummy Device ID (Word 1Dh) ....................................................................................... 57
4.5.1.7 Initialization Control 2 (Word 0Fh)................................................................................... 57
4.5.1.8 Software Defined Pins Control (Word 10h)........................................................................ 59
4.5.1.9 EEPROM Sizing & Protected Fields (Word 12h) .................................................................. 60
4.5.1.10 Initialization Control 3 (Word 14h, 24h) ........................................................................... 61
4.5.1.11 NC-SI and PCIe* Completion Timeout Configuration (Word 15h) ......................................... 63
4.5.1.12 MSI-X Configuration (Word 16h) ..................................................................................... 64
4.5.1.13 PLL/Lane/PHY Initialization Pointer (Word 17h) ................................................................. 64
4.5.1.14 PCIe* Initialization Configuration 1 (Word 18h)................................................................. 64
4.5.1.15 PCIe* Initialization Configuration 2 (Word 19h)................................................................. 64
4.5.1.16 Software Defined Pins Control (Word 20h)........................................................................ 65
4.5.1.17 PCIe* Initialization Configuration 3 (Word 1Ah)................................................................. 66
4.5.1.18 PCIe* Control (Word 1Bh).............................................................................................. 68
4.5.1.19 LED 1, 3 Configuration Defaults (Word 1Ch) ..................................................................... 69
4.5.1.20 Device Revision ID (Word 1Eh) ....................................................................................... 70
4.5.1.21 LED 0, 2 Configuration Defaults (Word 1Fh)...................................................................... 70
4.5.1.22 Functions Control (Word 21h) ......................................................................................... 72
4.5.1.23 LAN Power Consumption (Word 22h) ............................................................................... 72
4.5.1.24 Management Hardware Configuration Control (Word 23h) .................................................. 72
4.5.1.25 End of RO Area (Word 2Ch ............................................................................................. 74
4.5.1.26 Start of RO Area (Word 2Dh) .......................................................................................... 74
4.5.1.27 Watchdog Configuration (Word 2Eh)................................................................................ 74
4.5.1.28 VPD Pointer (Word 2Fh) ................................................................................................. 74
4.5.1.29 PXE Words (Words 30h:3Eh) .......................................................................................... 74
4.5.1.29.1 Main Setup Options PCI Function 0 (Word 30h) .............................................................. 74
4.5.1.29.2 Configuration Customization Options PCI Function 0 (Word 31h) ...................................... 76
4.5.1.29.3 PXE Version (Word 32h)............................................................................................ 77
4.5.1.29.4 IBA Capabilities (Word 33h) ........................................................................................ 77
4.5.1.29.5 Setup Options PCI Function 1 (Word 34h) ..................................................................... 77
4.5.1.29.6 Configuration Customization Options PCI Function 1 (Word 35h) ...................................... 78
4.5.1.29.7 iSCSI Option ROM Version (Word 36h).......................................................................... 78
4.5.1.29.8 Alternate MAC Address Pointer (Word 37h).................................................................... 78
4.5.1.29.9 Setup Options PCI Function 2 (Word 38h) ..................................................................... 78
4.5.1.29.10 Configuration Customization Options PCI Function 2 (Word 39h) ...................................... 78
4.5.1.29.11 Setup Options PCI Function 3 (Word 3Ah) ..................................................................... 78
4.5.1.29.12 Configuration Customization Options PCI Function 3 (Word 3Bh) ...................................... 78
4.5.1.29.13 iSCSI Boot Configuration Offset (Word 3Dh) .................................................................. 78
4.5.1.29.13.1 iSCSI Module Structure ........................................................................................ 78
4.5.1.29.14 Checksum Word (Word 3Fh)........................................................................................ 80
4.6 Manageability Control Sections .................................................................................................... 81
4.6.1 Sideband Configuration Structure .......................................................................................... 81
4.6.1.1 Section Header - (0ffset 0h) ........................................................................................... 81
4.6.1.2 SMBus Max Fragment Size - (0ffset 01h).......................................................................... 81
4.6.1.3 SMBus Notification Timeout and Flags - (0ffset 02h) .......................................................... 81