Filter
Top Products
Intel
®
82575EB Gigabit Ethernet Controller — Link Mode/Configuration
Intel
®
82575EB Gigabit Ethernet Controller 324632-003
Software Developer’s Manual and EEPROM Guide Revision: 2.1
282 January 2011
To avoid this contention, accesses from both LAN devices MUST be synchronized using external
software synchronization of the memory or I/O transactions responsible for the access. It might be
possible to ensure contention-avoidance simply by nature of software sequentially.
13.4 Link Mode/Configuration
The 82575 provides significant amount of flexibility in pairing a LAN device with a particular type of
media (copper or fiber-optic) as well as the specific transceiver/interface used to communicate with the
media. Each MAC, representing a distinct LAN device, can be coupled with an internal copper PHY (the
default) or SerDes interface independently. The link configuration specified for each LAN device can be
specified in the LINK_MODE field of the Extended Device Control Register (CTRL_EXT) and initialized
from the EEPROM Initialization Control Word 3 associated with each LAN device
13.5 LAN Disable
For a LOM design, it might be desirable for the system to provide BIOS-setup capability for selectively
enabling or disabling LOM devices. This might allow an end-user more control over system resource-
management, avoid conflicts with add-in NIC solutions, etc. The 82575 provides support for selectively
enabling or disabling one or both LAN device(s) in the system.
13.5.1 Overview
Device presence (or non-presence) must be established early during BIOS execution in order to ensure
that BIOS resource-allocation (of interrupts, of memory or IO regions) is done according to devices that
are present only. This is frequently accomplished using a BIOS CVDR (Configuration Values Driven on
Reset) mechanism. The 82575 LAN-disable mechanism is implemented in order to be compatible with
such a solution. The 82575 samples two pins (strapping) on PCIe* reset to determine the LAN-enable
configuration. The 82575 also enables the same through EEPROM presetting.
The LAN disabling can be done at two different levels. Either the LAN is disabled completely, or the
function is not apparent on the PCIe* configuration space. In this case, the LAN function is still available
for the manageability accesses. The selection between the two modes is done using the
PHY_in_LAN_disable EEPROM bit.
When a particular LAN is fully disabled, all internal clocks to that LAN are disabled, the 82575 is held in
reset, and the internal PHY for that LAN is powered-down. In both modes, The 82575 does not respond
to PCI configuration cycles, unless it is function #0, in which case, the function presents itself as a
dummy device. Effectively, the LAN device becomes invisible to the system from both a configuration
and power-consumption standpoint.
As mentioned all PCI functions can be enabled or disabled and an additional EEPROM bit (LAN Function
Sel) enables to swap between the two LAN functions.
It is desired to keep all the functions at their respective location, even when other functions are
disabled. If function #0 (either LAN0 or LAN1) is disabled, then it does not disappear from the PCIe*
configuration space. Rather, the function presents itself as a dummy function. The device ID and class