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Manageability EEPROM Control Register - EEMNGCTL (01010h; RO) — Intel
®
82575EB Gigabit
Ethernet Controller
324632-003 Intel
®
82575EB Gigabit Ethernet Controller
Revision: 2.1 Software Developer’s Manual and EEPROM Guide
January 2011 335
14.3.24 Manageability EEPROM Control Register -
EEMNGCTL (01010h; RO)
This register is reserved for firmware access to the EEPROM and is read-only by the host.
NC-SI Clock
and I/O Pads
Strength
10:9 00b Reflects the NC-SI clock and I/O pad drive strength settings in bits
15:14 of EEPROM word 15h.
SDP_IDDQ_EN 11 0b Reflects SDP behavior in the dynamic IDDQ setting in bit 6 of EEPROM
word Ah.
EEPROM
Parallel State
13:12 X State of the EEPROM parallel access arbitration state machine.
EEPROM Serial
State
15:14 X State of the EEPROM serial access arbitration state machine.
Flash Serial
State
17:16 X State of the Flash serial access arbitration state machine.
Flash Read
Data State
19:18 X State of the Flash read data bus arbitration state machine.
Flash Parallel
State
22:20 X State of the Flash parallel access arbitration state machine.
Reserved 30:23 0h Reserved
Deadlock
Release
31 X Indicates a deadlock condition was detected in the EEPROM and the
current grant was released.
Field Bit(s)
Initial
Value
Description
Reserved 17:0 00h Reserved
CFG_DONE 0 18 0b MNG Configuration Cycle is Done for Port 0
This bit indicates that the MNG configuration cycle (SerDes, PHY, GIO and PLLs) is
done for port 0.
This bit is set to 1b by MNG firmware to indicate that the configuration is done
and cleared by hardware on any of the reset sources that cause the firmware to
init the PHY. Writing a 0b by firmware does not affect the state of this bit.
Note: The Port 0 software device driver should not try to access the PHY for
configuration before this bit is set (see Section 3.0).
CFG_DONE 1 19 0b MNG Configuration Cycle is Done for Port 1
This bit indicates that the MNG configuration cycle (SerDes, PHY, GIO and PLLs) is
done for port 1.
This bit is set to 1b by MNG firmware to indicate that the configuration is done
and cleared by hardware on any of the reset sources that cause the firmware to
init the PHY. Writing a 0b by firmware does not affect the state of this bit.
Note: The Port 1 software device driver should not try to access the PHY for
configuration before this bit is set (see Section 3.0).
Reserved 31:20 00h Reserved