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Intel
®
82575EB Gigabit Ethernet Controller — Good Octets Received Count - GORCL (04088h;
RC)/GORCH (0408Ch; RC)
Intel
®
82575EB Gigabit Ethernet Controller 324632-003
Software Developer’s Manual and EEPROM Guide Revision: 2.1
424 January 2011
14.9.29 Good Octets Received Count - GORCL (04088h;
RC)/GORCH (0408Ch; RC)
These registers make up a 64-bit register that counts the number of good (no errors) octets received.
This register includes bytes received in a packet from the <Destination Address> field through the
<CRC> field, inclusively. This register resets each time the upper 32 bits are read (GORCH).
In addition, it sticks at FFFFh_FFFFh_FFFFh_FFFFh when the maximum value is reached. Only octets of
packets that pass address filtering are counted in this register. This register does not count octets of
packets counted by the Missed Packet Count (MPC) register. Octets of packets sent to the manageability
engine are included in this counter. This register only increments if receives are enabled.
These octets do not include octets of received flow control packets.
14.9.30 Good Octets Transmitted Count - GOTCL
(04090h; RC)/ GOTCH (04094; RC)
These registers make up a 64-bit register that counts the number of good (no errors) packets
transmitted. This register must be accessed using two independent 32-bit accesses. This register resets
each time the upper 32 bits are read (GOTCH).
In addition, it sticks at FFFF_FFFF_FFFF_FFFFh when the maximum value is reached. This register
includes bytes transmitted in a packet from the <Destination Address> field through the <CRC> field,
inclusively. This register counts octets in successfully transmitted packets that are 64 or more bytes in
length. This register only increments if transmits are enabled. The register counts clear as well as
secure octets.
These octets do not include octets in transmitted flow control packets.
14.9.31 Receive No Buffers Count - RNBC (040A0h; RC)
This register counts the number of times that frames were received when there were no available
buffers in host memory to store those frames (receive descriptor head and tail pointers were equal).
The packet is still received if there is space in the FIFO. This register only increments if receives are
enabled.
This register does not increment when flow control packets are received.
Field Bit(s)
Initial
Value
Description
GORCL 31:0 0b Number of good octets received – lower 4 bytes.
GORCH 31:0 0b Number of good octets received – upper 4 bytes.
Field Bit(s)
Initial
Value
Description
GOTCL 31:0 0b Number of good octets transmitted – lower 4 bytes.
GOTCH 31:0 0b Number of good octets transmitted – upper 4 bytes.