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Extended Device Control Register - CTRL_EXT (00018h, R/W) — Intel
®
82575EB Gigabit Ethernet
Controller
324632-003 Intel
®
82575EB Gigabit Ethernet Controller
Revision: 2.1 Software Developer’s Manual and EEPROM Guide
January 2011 307
Field Bit(s)
Initial
Value
Description
NSICR 0 0b Non Selective Interrupt clear on read
When set, every read of ICR clears it. When this bit is cleared, an ICR read
causes it to be cleared only if an actual interrupt was asserted or IMS = 0b.
This bit should be cleared by software device drivers not using the extended
interrupts capabilities and set otherwise.
Reserved 1 0b Reserved. Should be written as 0b to ensure future compatibility.
SDP2_GPIEN 2 0b General Purpose Interrupt Detection Enable for SDP2
If software-controllable IO pin SDP2 is configured as an input, this bit (when
set to 1b) enables use for GPI interrupt detection.
SDP3_GPIEN 3 0b General Purpose Interrupt Detection Enable for SDP3
If software-controllable IO pin SDP3 is configured as an input, this bit (when
set to 1b) enables use for GPI interrupt detection.
Reserved 5:4 00b Reserved.
Reads as 00b.
SDP2_DATA 6 0b
1
SDP2 Data Value. Used to read (write) the value of software-controllable IO
pin SDP2. If SDP2 is configured as an output (SDP2_IODIR = 1b), this bit
controls the value driven on the pin (initial value EEPROM-configurable). If
SDP2 is configured as an input, reads return the current value of the pin.
SDP3_DATA 7 0b
1
SDP3 Data Value. Used to read (write) the value of software-controllable IO
pin SDP3. If SDP3 is configured as an output (SDP3_IODIR = 1b), this bit
controls the value driven on the pin (initial value EEPROM-configurable). If
SDP3 is configured as an input, reads return the current value of the pin.
Reserved 9:8 0b
1
Reserved
Formally used as SDP5 and SDP4 pin input/output direction control,
respectively.
SDP2_IODIR 10 0b
1
SDP2 Pin Directionality. Controls whether software-controllable pin SDP2 is
configured as an input or output (0b = input, 1b = output). Initial value is
EEPROM-configurable. This bit is not affected by software or system reset,
only by initial power-on or direct software writes.
SDP3_IODIR 11 0b
1
SDP3 Pin Directionality. Controls whether software-controllable pin SDP3 is
configured as an input or output (0b = input, 1b = output). Initial value is
EEPROM-configurable. This bit is not affected by software or system reset,
only by initial power-on or direct software writes.
ASDCHK 12 0b ASD Check
Initiates an Auto-Speed-Detection (ASD) sequence to sense the frequency of
the PHY receive clock (RX_CLK). The results are reflected in STATUS.ASDV.
This bit is self-clearing.
EE_RST 13 0b EEPROM Reset
When set, initiates a reset-like event to the EEPROM function. This causes the
EEPROM to be read as if a RST# assertion had occurred. All 82575 functions
should be disabled prior to setting this bit. This bit is self-clearing.
RESERVED 14 0b Reserved. Should be set to 0b.
SPD_BYPS 15 0b Speed Select Bypass
When set to 1b, all speed detection mechanisms are bypassed, and the 82575
is immediately set to the speed indicated by CTRL.SPEED. This provides a
method for software to have full control of the speed settings of the 82575
and when the change takes place by overriding the hardware clock switching
circuitry.
NS_DIS 16 0 No Snoop Disable
When set to 1b, the 82575 does not set the no snoop attribute in any PCIe*
packet, independent of PCIe* configuration and the setting of individual no
snoop enable bits. When set to 0b, behavior of no snoop is determined by
PCIe* configuration and the setting of individual no snoop enable bits.