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Power Management Interconnects — Intel
®
82575EB Gigabit Ethernet Controller
324632-003 Intel
®
82575EB Gigabit Ethernet Controller
Revision: 2.1 Software Developer’s Manual and EEPROM Guide
January 2011 219
Figure 24. Link Power Management
7.4.0.2 NC-SI Clock Control
The 82575 can be configured to provide a 50 MHz output clock to its NC-SI interface and other platform
devices. When enabled (through the NC-SI Output Clock EEPROM bit), the NC-SI clock is provided in all
power states without exception.
7.4.0.3 PHY Power Management
7.4.0.3.1 Link Speed Control
Normal PHY speed negotiation drives to establish a link at the highest possible speed. The 82575
supports an additional mode of operation where the PHY drives to establish a link at a low speed. The
link-up process allows a link to come up at the lowest possible speed in cases where power is more
important than performance. Different behavior is defined for the D0 state and the other non-D0
states.
Note: The Low Power Link Up (LPLU) feature just described should be disabled (in both D0a and
non-D0a states) when the user advertisement is anything other than 10/100/1000 Mb/s.