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Total Octets Received - TORL (040C0h; RC) / TORH (040C4h; RC) — Intel
®
82575EB Gigabit
Ethernet Controller
324632-003 Intel
®
82575EB Gigabit Ethernet Controller
Revision: 2.1 Software Developer’s Manual and EEPROM Guide
January 2011 427
14.9.39 Total Octets Received - TORL (040C0h; RC) /
TORH (040C4h; RC)
These registers make up a logical 64-bit register which counts the total number of octets received.
This register must be accessed using two independent 32-bit accesses. This register resets each time
the upper 32 bits are read (TORH). In addition, it sticks at FFFF_FFFF_FFFF_FFFFh when the maximum
value is reached.
All packets received have their octets summed into this register, regardless of their length, whether
they are erred, or whether they are flow control packets. This register includes bytes received in a
packet from the <Destination Address> field through the <CRC> field, inclusively. This register only
increments if receives are enabled.
Note: Broadcast rejected packets are counted in this counter (as opposed to all other rejected
packets that are not counted).
14.9.40 Total Octets Transmitted - TOTL (040C8h; RC /
TOTH (040CCh; RC)
These registers make up a 64-bit register that counts the total number of octets transmitted. This
register must be accessed using two independent 32-bit accesses. This register resets each time the
upper 32 bits are read (TOTH). In addition, it sticks at FFFF_FFFF_FFFF_FFFFh when the maximum
value is reached.
All transmitted packets have their octets summed into this register, regardless of their length or
whether they are flow control packets. This register includes bytes transmitted in a packet from the
<Destination Address> field through the <CRC> field, inclusively.
Octets transmitted as part of partial packet transmissions (for example, collisions in half-duplex mode)
are not included in this register. This register only increments if transmits are enabled.
14.9.41 Total Packets Received - TPR (040D0h; RC)
This register counts the total number of all packets received. All packets received are counted in this
register, regardless of their length, whether they have errors, or whether they are flow control packets.
This register only increments if receives are enabled.
Note: Broadcast rejected packets are counted in this counter (as opposed to all other rejected
packets that are not counted).
TPR can count packets interrupted by a link disconnect although they have a CRC error.
Field Bit(s)
Initial
Value
Description
TORL 31:0 0b Number of total octets received – lower 4 bytes.
TORH 31:0 0b Number of total octets received – upper 4 bytes.
Field Bit(s)
Initial
Value
Description
TOTL 31:0 0b Number of total octets transmitted – lower 4 bytes.
TOTH 31:0 0b Number of total octets transmitted – upper 4 bytes.