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Multicast Table Array - MTA (05200h + 4*n [n..127]; R/W) — Intel
®
82575EB Gigabit Ethernet
Controller
324632-003 Intel
®
82575EB Gigabit Ethernet Controller
Revision: 2.1 Software Developer’s Manual and EEPROM Guide
January 2011 379
14.5.1 Multicast Table Array - MTA (05200h + 4*n
[n..127]; R/W)
There is one register per 32 bits of the Multicast Address Table for a total of 128 registers (the
MTA[127:0] designation). Software must mask to the desired bit on reads and supply a 32-bit word on
writes. The first bit of the address used to access the table is set according to the RX_CTRL.MO field.
Note: All accesses to this table must be 32 bit.
Figure 33 shows the multicast lookup algorithm. The destination address shown represents the
internally stored ordering of the received DA. Note that bit 0 indicated in this diagram is the first on the
wire.
Figure 33. Multicast Table Array
Field Bit(s)
Initial
Value
Description
Bit Vector 31:0 X Word wide bit vector specifying 32 bits in the multicast address
filter table.
47:40 39:32 31:24 23:16 15:8 7:0
pointer[11:5]
Multicast Table Arra
y
32 x 128
(4096 bit vector)
...
...
pointer[4:0]
word
bit
?
Destination Address
RCTL.MO[1:0]