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Intel
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82575EB Gigabit Ethernet Controller — Receive Data Flow
Intel
®
82575EB Gigabit Ethernet Controller 324632-003
Software Developer’s Manual and EEPROM Guide Revision: 2.1
102 January 2011
5.2 Receive Data Flow
Receive Data Flow provides a high level description of all data/control transformations steps needed for
receiving Ethernet packets over the wire.
5.3 Receive Functionality
Packet reception consists of recognizing the presence of a packet on the wire, performing address
filtering, storing the packet in the receive data FIFO, transferring the data to one of the four receive
queues in host memory, and updating the state of a receive descriptor.
Note: The maximum supported received packet size is 9018 bytes.
Step Description
13 After enough descriptors are gathered for write-back or the interrupt moderation timer completes, the
descriptors are written back to host memory using PCIe* posted writes. Alternatively, the header pointer might
only be written back.
14 After the interrupt moderation timer completes, an interrupt is generated to notify the host driver that the
specific packet has been read to the 82575and the driver can release the buffers.
Step Description
1 The host creates a descriptor ring and configures one of the 82575's receive queues with the address location,
length, head and tail pointers of the ring (one of four available Rx queues).
2 The host initializes descriptors that point to empty data buffers. The host places these descriptors in the
correct location at the appropriate receive ring.
3 The host updates the appropriate queue tail pointer (RDT).
4 the 82575’s DMA senses a change of a specific RDT and as a result sends a PCIe* request to fetch the
descriptors from host memory.
5 The descriptors content is received in a PCIe* read completion and is written to the appropriate location in the
descriptor queue internal cache.
6 A packet enters the receive MAC.
7 The MAC forwards the packet to receive filter(s).
8 If the packet matches the pre-programmed criteria of the receive filtering it is forwarded to receive FIFO.
9 The receive DMA fetches the next descriptor from the appropriate queue to be used for the next received
packet.
10 After the entire packet is placed into the receive FIFO, the receive DMA posts the packet data to the location
indicated by the descriptor through the PCIe* interface. If the packet size is greater than the buffer size,
more descriptors are fetched and their buffers are used for the received packet.
11 When the packet is placed into host memory the receive DMA updates all the descriptor(s) that were used by
packet data.
12 After enough descriptors are gathered for write-back, the interrupt moderation timer completes, or the packet
requires immediate forwarding, the receive DMA writes back the descriptor content along with status bits that
indicate the packet information including what offloads were done on the packet.
13 After the interrupt moderation timer completes or an immediate packet is received, the 82575 initiates an
interrupt to the host to indicate that a new received packet is ready in host memory.
14 The host reads packet data and sends it to the TCP/IP stack for further processing. The host releases the
associated buffers and descriptors once they are no longer in use.