Filter
Top Products
Intel
®
82575EB Gigabit Ethernet Controller — Content
Intel
®
82575EB Gigabit Ethernet Controller 324632-003
Software Developer’s Manual and EEPROM Guide Revision: 2.1
14 January 2011
14.3.26 Manageability Flash Control Register - FLMNGCTL (1018h; R/W).............................................. 336
14.3.27 Manageability Flash Read Data - FLMNGDATA (101Ch; R/W) ................................................... 336
14.3.28 Manageability Flash Read Counter - FLMNGCNT (1020h; R/W)................................................. 337
14.3.29 EEPROM Auto Read Bus Control - EEARBC (01024h; R/W) ...................................................... 337
14.3.30 Watchdog Setup - WDSTP (01040h; R/W) ............................................................................ 338
14.3.31 Watchdog SW Device Status - WDSWSTS (01044h; R/W) ....................................................... 338
14.3.32 Free Running Timer - FRTIMER (01048h; RWS) ..................................................................... 339
14.3.33 TCP Timer - TCPTIMER (0104Ch; R/W)................................................................................. 339
14.3.34 Interrupt Cause Read Register - ICR (000C0H; R).................................................................. 340
14.3.35 Interrupt Cause Set Register - ICS (000C8h; WO) ................................................................. 341
14.3.36 Interrupt Mask Set/Read Register - IMS (000D0h; R/W)......................................................... 342
14.3.37 Interrupt Mask Clear Register - IMC (000D8h; W).................................................................. 343
14.3.38 Interrupt Acknowledge Auto Mask Register - IAM (000E0h; R/W)............................................. 344
14.3.39 Extended Interrupt Cause - EICR (01580h; RC/W1C) ............................................................. 345
14.3.40 Extended Interrupt Cause Set - EICS (01520h; WO) .............................................................. 345
14.3.41 Extended Interrupt Mask Set/Read - EIMS (01524h; RWS) ..................................................... 346
14.3.42 Extended Interrupt Mask Clear - EIMC (01528h; WO)............................................................. 346
14.3.43 Extended Interrupt Auto Clear - EIAC (0152Ch; R/W)............................................................. 347
14.3.44 Extended Interrupt Auto Mask Enable - EIAM (01530h; R/W) .................................................. 347
14.3.45 Interrupt Throttle - EITR (01680h + 4*n [n = 0..9]; R/W) ...................................................... 348
14.3.46 Immediate Interrupt Rx - IMIR (05A80h + 4*n [n = 0..7]; R/W) ............................................. 349
14.3.47 Immediate Interrupt Rx Extended - IMIREXT (05AA0h + 4*n [n = 0..7]; R/W) .......................... 350
14.3.48 Immediate Interrupt Rx VLAN Priority - IMIRVP (05AC0h; R/W)............................................... 350
14.3.49 MSI-X Allocation - MSIXBM (01600h + 4*n [n = 0..9]; R/W)................................................... 351
14.3.50 Receive Control Register - RCTL (00100h; R/W) .................................................................... 351
14.3.51 Split and Replication Receive Control - SRRCTL (0280Ch + 100*n [n=0..3]; R/W) ..................... 354
14.3.52 Packet Split Receive Type - PSRTYPE (05480h + 4*n [n=0..3]; R/W) ....................................... 355
14.3.53 Flow Control Receive Threshold Low - FCRTL (02160h; R/W)................................................... 356
14.3.54 Flow Control Receive Threshold High - FCRTH (02168h; R/W) ................................................. 357
14.3.55 Flow Control Refresh Threshold Value - FCRTV (02460h; R/W) ................................................ 357
14.3.55.1 Receive Descriptor Base Address Low - RDBAL (02800h + 100*n [n=0..3]; R/W) .................358
14.3.56 Receive Descriptor Base Address High - RDBAH (02804h + 100*n [n=0..3]; R/W)..................... 358
14.3.57 Receive Descriptor Length - RDLEN (02808h + 100*n [n=0..3]; R/W)...................................... 358
14.3.58 Receive Descriptor Head - RDH (02810h + 100*n [n=0..3]; R/W) ........................................... 359
14.3.59 Receive Descriptor Tail - RDT (02818h + 100*n [n=0..3]; R/W) .............................................. 359
14.3.60 Receive Descriptor Control - RXDCTL (02828h + 100*n [n=0..3]; R/W).................................... 360
14.3.61 Receive Checksum Control - RXCSUM (05000h; R/W) ............................................................ 361
14.3.62 Receive Long Packet Maximum Length - RLPML (05004; R/W)................................................. 362
14.3.63 Receive Filter Control Register - RFCTL (05008h; R/W)........................................................... 362
14.3.64 Transmit Control Register - TCTL (00400h; R/W)................................................................... 363
14.3.65 Transmit Control Extended - TCTL_EXT (00404;R/W)............................................................. 364
14.3.66 Transmit IPG Register - TIPG (00410;R/W)........................................................................... 365
14.3.67 DMA Tx Control - DTXCTL (03590h; R/W)............................................................................. 365
14.3.68 Transmit Descriptor Base Address Low - TDBAL (03800h + 100*n [n=0..3]; R/W)..................... 366
14.3.69 Transmit Descriptor Base Address High - TDBAH (03804h + 100*n [n=0..3]; R/W).................... 366
14.3.70 Transmit Descriptor Length - TDLEN (03808h + 100*n [n=0..3]; R/W) .................................... 367
14.3.71 Transmit Descriptor Head - TDH (03810h + 100*n [n=0..3]; R/W) .......................................... 367
14.3.72 Transmit Descriptor Tail - TDT (03818h + 100*n [n=0..3]; R/W)............................................. 367
14.3.73 Transmit Descriptor Control - TXDCTL (03828h + 100*n [n=0..3]; R/W) .................................. 368
14.3.74 Tx Descriptor Completion Write-Back Address Low - TDWBAL (03838h + 100*n [n=0..3]; R/W).. 369
14.3.75 Tx Descriptor Completion Write-Back Address High - TDWBAH (0383Ch + 100*n [n=0..3]; R/W) 370
14.3.76 PCS Configuration 0 - PCS_CFG (04200h; R/W)..................................................................... 370
14.3.77 PCS Link Control - PCS_LCTL (04208h; R/W) ........................................................................ 371
14.3.78 PCS Link Status - PCS_LSTS (0420Ch; R/W)......................................................................... 372
14.3.79 AN Advertisement - PCS_ANADV (04218h; R/W) ................................................................... 373
14.3.80 Link Partner Ability - PCS_LPAB (0421Ch; RO) ...................................................................... 374
14.3.81 Next Page Transmit - PCS_NPTX (04220h; RO) ..................................................................... 375
14.3.82 Link Partner Ability Next Page - PCS_LPABNP (04224h; RO).................................................... 376
14.4 DCA Registers ......................................................................................................................... 376
14.4.1 Rx DCA Control Registers - RXCTL (02814h 100h *n [n=0..3]; R/W)........................................ 376