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Intel
®
82575EB Gigabit Ethernet Controller — Interrupts
Intel
®
82575EB Gigabit Ethernet Controller 324632-003
Software Developer’s Manual and EEPROM Guide Revision: 2.1
162 January 2011
Head write-back occurs if TDWBAL#.Head_WB_En is set for this queue and the RS bit is set in the Tx
descriptor, following corresponding data upload into packet buffer.
The software device driver has control on this feature through Tx Queue 0-3 head write-back address,
low and high (enabling a 64-bit address).
The low register’s LSB hold the control bits.
• The Head_WB_En bit enables activation of tail write-back. In this case, no descriptor write-back is
executed.
• The SN_WB_en bit enables both the DD and the sequence number bit write-back into the descriptor
address.
• The 30 upper bits of this register hold the lowest 32 bits of the head write-back address, assuming
that the two last bits are set to 0b.
The high register holds the high part of the 64-bit address. The 82575 only writes the 16 bits that are
pointed by TDWBAH/TDWBAL address.
5.13 Interrupts
The interrupt logic consists of the 10 registers listed in Table 49 plus the registers associated with MSI/
MSI-X signaling.
Table 49. Interrupt Registers
5.13.1 Interrupt Cause Register (ICR)
This register captures the interrupt causes not directly captured by the EICR. These are infrequent
management interrupts and error conditions.
Register Acronym Function
Interrupt Cause ICR Records interrupt conditions.
Interrupt Cause Set ICS Allows software to set bits in the ICR.
Interrupt Mask Set/Read IMS Sets or reads bits in the other interrupt mask.
Interrupt Mask Clear IMC Clears bits in the other interrupt mask.
Interrupt Acknowledge
auto-mask
IAM Under some conditions, the content of this register is copied to the mask register
following read or write of ICR.
Extended Interrupt
Cause
EICR ICR. Records interrupt causes from receive and transmit queues. An interrupt is
signaled when unmasked bits in this register are set.
Extended Interrupt
Cause Set
EICS Enables software to set bits in the ICR.
Extended Interrupt
Mask Set/Read
EIMS Sets or read bits in the interrupt mask.
Extended Interrupt
Mask Clear
EIMC Clears bits in the interrupt mask.
Extended Interrupt Auto
Clear
EIAC Enables bits in the EICR to be cleared automatically following an MSI-X interrupt
without a read or write of the EICR.
Extended Interrupt
Acknowledge Auto-Mask
EIAM This register is used to decide which masks are cleared in the extended mask
register following read or write of EICR or which masks are set following a write
to EICS. In MSI-X mode, this register also controls which bits in EIMC are cleared
automatically following an MSI-X interrupt.