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MSI-X Registers — Intel
®
82575EB Gigabit Ethernet Controller
324632-003 Intel
®
82575EB Gigabit Ethernet Controller
Revision: 2.1 Software Developer’s Manual and EEPROM Guide
January 2011 445
14.12 MSI-X Registers
These registers are used to configure the MSI-X mechanism. The address and upper address registers
sets the address for each of the vectors. The message register sets the data sent to the relevant
address. The vector control registers are used to enable specific vectors.
The pending bit array register indicates which vectors have pending interrupts.
The structure is listed in Table 93.
Table 93. MSI-X Table Structure
Note: N = 10.
Note: N = 10. As a result, only QWORD0 is implemented.
Data Mode 6:5 00b Data Mode
Defines the algorithm used to determine the data content:
00b = Constant: All the data is equal to PGCTL.data_const field.
01b = Incremental: Each word is incremented by 1 relative to the previous word. The
value of the first word of the packet is the packet index modulo 65356 (where the index
of the first packet sent after start is asserted is zero).
10b = Use 16-bit LFSR output. The polynomial of the LFSR is X^16 + X^10 + X^7 +
X^1 and the seed is16'hFFFF. The LFSR is shifted every 4th word and provides the
value for the next four words (for example, each four consecutive words have the same
value). The LFSR is reset when PGNP.Start is asserted, but is not reset between
packets.
11b = Reserved.
Stop on Error 7 0b Stop on Error
Stop sending packets when an error is found by the receive side.
Reserved 15:8 0h Reserved
Constant Data 31:16 0h Constant Data
The data used when Data Mode = 00b.
DWORD3 DWORD2 DWORD1 DWORD0
Vector Control Msg Data Msg Upper Addr Msg Addr Entry 0 Base
Vector Control Msg Data Msg Upper Addr Msg Addr Entry 1 Base + 1*16
Vector Control Msg Data Msg Upper Addr Msg Addr Entry 2 Base + 2*16
… … … … …
Vector Control Msg Data Msg Upper Addr Msg Addr Entry (N-1) Base + (N-1) *16
63:0
Pending Bits 0 through 63 QWORD0 Base
Pending Bits 64 through 127 QWORD1 Base+1*8
…… …
Pending Bits ((N-1) div 64)*64 through
N-1
QWORD((N-1) div 64) BASE + ((N-1) div 64)*8