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Software-Firmware Synchronization - SW_FW_SYNC (05B5Ch; R/WS) — Intel
®
82575EB Gigabit
Ethernet Controller
324632-003 Intel
®
82575EB Gigabit Ethernet Controller
Revision: 2.1 Software Developer’s Manual and EEPROM Guide
January 2011 413
Notes:
1. This register should be written only by the manageability firmware. The device driver should only read this register.
2. Firmware ignores the EEPROM semaphore in operating system hung states.
3. Bits 15:0 are cleared on firmware reset.
14.8.21 Software-Firmware Synchronization -
SW_FW_SYNC (05B5Ch; R/WS)
This register is used to synchronize software and firmware. Note that this register is common to both
ports 0 and 1.
14.8.21.1 Using the Software-Firmware Synchronization
Register
Under reset conditions:
• The software-controlled bits (15:0) are reset as any other CSR (for example, on global resets,
D3hot exit, software reset, and forced TCO). Software is expected to clear the bits on entry to D3
state.
• The firmware-controlled bits (31:16) are reset after an Internal_Power_On_Reset and firmware
reset.
Reserved 5:4 00b Reserved
FW_Mode 3:1 0h Firmware Mode
Indicates the firmware mode as follows:
000b = No MNG.
010b = PT mode.
011b = Reserved.
100b = Host Interface enable only.
EEP_FW_
Semaphore
0 0h EEPROM Firmware Semaphore
Firmware should set this bit to 1b before accessing the EEPROM. If software using
the SWSM does not lock the EEPROM, firmware is able to set this bit to 1b. Firmware
should set this bit to 0b after completing EEPROM access.
Field Bit(s)
Initial
Value
Description
SW_EEP_SM 0 0b When set to 1b, EEPROM access is owned by software.
SW_PHY_SM0 1 0b When set to 1b, PHY 0 access is owned by software.
SW_PHY_SM1 2 0b When set to 1b, PHY 1 access is owned by software.
SW_MAC_CSR_SM 3 0b When set to 1b, software owns access to shared CSRs.
Reserved 15:4 00h Reserved
FW_EEP_SM 16 0b When set to 1b, EEPROM access is owned by firmware.
FW_PHY_SM0 17 0b When set to 1b, PHY 0 access is owned by firmware.
FW_PHY_SM1 18 0b When set to 1b, PHY 1 access is owned by firmware.
FW_MAC_CSR_SM 19 0b When set to 1b, firmware owns access to shared CSRs.
Reserved 31:20 0b Reserved for future use.