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Defer Count - DC (04030h; RC) — Intel
®
82575EB Gigabit Ethernet Controller
324632-003 Intel
®
82575EB Gigabit Ethernet Controller
Revision: 2.1 Software Developer’s Manual and EEPROM Guide
January 2011 419
14.9.11 Defer Count - DC (04030h; RC)
This register counts defer events. A defer event occurs when the transmitter cannot immediately send
a packet due to the medium being busy either because another device is transmitting, the IPG timer
has not expired, half-duplex deferral events, reception of XOFF frames, or the link is not up. This
register only increments if transmits are enabled. This counter does not increment for streaming
transmits that are deferred due to TX IPG.
14.9.12 Transmit with No CRS - TNCRS (04034h; RC)
This register counts the number of successful packet transmission in which the CRS input from the PHY
was not asserted within one slot time of start of transmission from the MAC. Start of transmission is
defined as the assertion of TX_EN to the PHY.
The PHY should assert CRS during every transmission. Failure to do so might indicate that the link has
failed, or the PHY has an incorrect link configuration. This register only increments if transmits are
enabled. This register is not valid in SGMII mode and is only valid when the 82575 is operating at half
duplex.
14.9.13 Receive Length Error Count - RLEC (04040h;
RC)
This register counts receive length error events. A length error occurs if an incoming packet passes the
filter criteria but is undersized or oversized. Packets less than 64 bytes are undersized. Packets over
1518/1522/1526 bytes (according to the number of VLAN tags present) are oversized if Long Packet
Enable (LPE) is 0b. If LPE is 1b, then an incoming, packet is considered oversized if it exceeds the size
defined in RLPML.PML field.
If receives are not enabled, this register does not increment. These lengths are based on bytes in the
received packet from <Destination Address> through <CRC>, inclusively.
14.9.14 XON Received Count - XONRXC (04048h; RC)
This register counts the number of valid XON packets received. XON packets can use the global
address, or the station address. This register only increments if receives are enabled.
Field Bit(s)
Initial
Value
Description
CDC 31:0 0b Number of defer events.
Field Bit(s)
Initial
Value
Description
TNCRS 31:0 0b Number of transmissions without a CRS assertion from the PHY.
Field Bit(s)
Initial
Value
Description
RLEC 31:0 0b Number of packets with receive length errors.