Filter
Top Products
Intel
®
82575EB Gigabit Ethernet Controller — Power-State Transitions Timing
Intel
®
82575EB Gigabit Ethernet Controller 324632-003
Software Developer’s Manual and EEPROM Guide Revision: 2.1
226 January 2011
7.4.2 Power-State Transitions Timing
The following sections give detailed timing for the state transitions. The timing diagrams are not to
scale, and the dotted connecting lines represent the 82575 requirements, and the solid connecting
lines, 82575 guarantees. The clocks edges are shown to indicate running clocks only. They are not used
to indicate the actual number of cycles for any operation.
7.4.2.1 Power Up (Off to Dup to D0u to D0a)
Notes
1 Xosc is stable t
xog
after the power is stable.
2 Internal_Power_On_Reset is asserted after all power supplies are good and t
ppg
, after Xosc, is stable.
3 An EEPROM read starts on the rising edge of Internal_Power_On_Reset.
4 After reading the EEPROM, the PHY reset is de-asserted.
5 APM wake-up mode may be enabled based on what is read from the EEPROM.
6 The PCIe* reference clock is valid t
PWRGDPE_RST-CLK
before the assertion of PE_RST_N.
Per the PCIe* Specification.
7 PE_RST_N is asserted t
PVPGL
after power is stable.
8 The Internal PCIe* clock is valid and stable t
ppg-clkint
from PE_RST_N de-assertion.
9 The PCIe* internal PE_RST_N signal is asserted t
clkpr
after the external PE_RST_N signal.
10 Assertion of the internal PCIe* PE_RST_N causes the EEPROM to be re-read, asserts PHY reset, and disables wake up.
11 After reading the EEPROM, PHY reset is de-asserted.
12 Link training starts after t
pgtrn
from PE_RST_N de-assertion.
Internal PCIe*
Clock (2.5 GHz)
Internal PwrGd (PLL)
DState
D0u
Reading EEPROM
D0a
PHY Reset
PCIe* Link Up
L0
Wakeup Enabled
4
5
7
Dr
10
11
12
3
5
APM/SMBus Wakeup
Power
Internal Power On
Reset
2
PCIe*
Reference Clock
PwrGd (PCIe*)
Read
3GIO
Read
rest
Read
3GIO
Read
rest
Xosc
1
6
8
txog
tee tee
9
tppg-clkint
13 14
PHY Power State Iddq Power-managed (Iddq or reduced link speed)
On
APM/SMBus Wakeup
tpgtrn
15
tpgres
tpgcfg
tPWRGD-CLK
tPVPGL
tppg
tclkpr