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Intel
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82575EB Gigabit Ethernet Controller — Dynamic Queue Enabling and Disabling
Intel
®
82575EB Gigabit Ethernet Controller 324632-003
Software Developer’s Manual and EEPROM Guide Revision: 2.1
32 January 2011
• Set the length register to the size of the descriptor ring.
• Program the TXDCTL register with the desired TX descriptor write back policy. Suggested values
are:
— WTHRESH = 1b
— All other fields 0b.
• Set the queue priority using TXDCTL.Priority
• Enable the queue using TXDCTL.ENABLE (queue zero is enabled by default).
Enable the transmit path by setting TCTL. This should be done only after all other settings are done.
3.6.1 Dynamic Queue Enabling and Disabling
Transmit queues can be dynamically enabled or disabled provided the following procedure is followed:
Enabling: Follow the per queue initialization previously described.
Disabling:
• Stop storing packet for transmission in this queue.
• Wait until the head of the queue (TDH) is equal to the tail (TDT). For example, the queue is empty.
• Disable the queue by clearing TXDCTL.ENABLE.
The Tx path can be disabled only after all Tx queues are disabled.
3.7 Link Setup Mechanisms and Control/Status
Bit Summary
Note: The CTRL_EXT.LINK_MODE value should be set to the desired mode prior to the setting of
the other fields in the link setup procedures.
3.7.1 PHY Initialization
Refer to the PHY documentation for the initialization and link setup steps. The software device driver
uses the MDIC register to initialize the PHY and setup the link.
3.7.2 MAC/PHY Link Setup (CTRL_EXT.LINK_MODE =
00b)
This section summarizes the various means of establishing proper MAC/PHY link setups, differences in
MAC CTRL register settings for each mechanism, and the relevant MAC status bits. The methods are
ordered in terms of preference (the first mechanism being the most preferred).
• MAC settings automatically based on duplex and speed resolved by PHY
(CTRL.FRCDPLX = 0b, CTRL.FRCSPD = 0b)