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DCA — Intel
®
82575EB Gigabit Ethernet Controller
324632-003 Intel
®
82575EB Gigabit Ethernet Controller
Revision: 2.1 Software Developer’s Manual and EEPROM Guide
January 2011 239
8.0 DCA
This section describes the Direct Cache Access (DCA) functionality for the 82575.
Direct Cache Access (DCA) is a method to improve network I/O performance by placing some posted
inbound writes directly within processor cache. DCA can significantly reduce processor cache miss
rates.
DCA provides a mechanism where the posted write data from an I/O device, such as an Ethernet NIC,
can be placed into the processor cache with a hardware pre-fetch. This mechanism is initialized upon a
power good reset. A software device driver for the I/O device configures it for DCA and sets up the
appropriate processor ID and bus ID for the device to send data. The device then encapsulates that
information in PCIe* TLP headers (in the TAG field) to trigger a hardware pre-fetch by the MCH to the
processor cache.
DCA implementation is controlled by separate registers (RXCTL and TXCTL) for each receive and
transmit queues. In addition, a DCA-enable bit can be found in the GCR register and a DCA_ID register
can be found for each port in order to make visible the function, device, and bus numbers to the
software device driver.
The RXCTL and TXCTL registers can be written by software and can be changed at any time. When
software changes the register contents, hardware applies changes only after all the previous packets in
progress for DCA has completed.
In order to implement DCA, the 82575 has to be aware of the data movement engine version being
used. The software device driver initializes the 82575 to make it aware of the data movement engine
version. DCA_BUS_SELECT CTRL is used in order to properly define the system configuration.
There are two modes for DCA implementation:
1. Data Movement Engine 1: The DCA target ID is derived from processor ID
2. Data Movement Engine 2: The DCA target ID is derived from APIC ID.
The software device driver selects one of these modes through the DCA Mode register.
8.1 Implementation Details
8.1.1 PCIe* Message Format for DCA (MWr Mode)
Figure 25 shows the format of the PCIe* message for DCA.