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Link Width — Intel
®
82575EB Gigabit Ethernet Controller
324632-003 Intel
®
82575EB Gigabit Ethernet Controller
Revision: 2.1 Software Developer’s Manual and EEPROM Guide
January 2011 187
The max link width is loaded into the Maximum Link Width field of the PCIe* Capability register
(LCAP[11:6]). The hardware default is the x4 link.
During link configuration, the platform and the 82575 negotiate on a common link width. The link width
must be one of the supported PCIe* link widths (1x, 2x, 4x), such that:
• If Maximum Link Width = x4, then the 82575 negotiates to either x4, x2 or x1
• If Maximum Link Width = x2, then the 82575 negotiates to either x2 or x1
• If Maximum Link Width = x1, then the 82575 only negotiates to x1
6.6.1.1 Polarity Inversion
If polarity inversion is detected, the Receiver must invert the received data.
During the training sequence, the Receiver looks at Symbols 6-15 of TS1 and TS2 as the indicator of
Lane polarity inversion (D+ and D- are swapped). If Lane polarity inversion occurs, the TS1 Symbols 6-
15 received are D21.5 as opposed to the expected D10.2. Similarly, if Lane polarity inversion occurs,
Symbols 6-15 of the TS2 ordered set are D26.5 as opposed to the expected D5.2. This provides the
clear indication of Lane polarity inversion.
6.6.1.2 L0s Exit latency
The number of FTS sequences (N_FTS) sent during L0s exit, is loaded from the EEPROM.
6.6.1.3 Lane-to-Lane De-Skew
A multi-lane link can have many sources of lane to lane skew. Although symbols are transmitted
simultaneously on all lanes, they cannot be expected to arrive at the receiver without lane-to-lane
skew. The lane-to-lane skew may include components, which are less than a bit time, bit time units
(400 ps for 2.5 Gb), or full symbol time units (4 ns) of skew caused by the retiming repeaters’ insert/
delete operations. Receivers use TS1 or TS2 or Skip ordered sets (SOS) to perform link de-skew
functions.
The 82575 supports de-skew of up to 6 symbols time (24 ns).
6.6.1.4 Lane Reversal
The following lane reversal modes are supported:
• Lane configuration of x4, x2, and x1
• Lane reversal in x4 and in x2
• Degraded mode (downshift) from x4 to x2 to x1 and from x2 to x1, with one restriction: if lane
reversal is executed in x4, then downshift is only to x1 and not to x2.
Note: The above restriction requires that a x2 interface to the 82575 must connect to lanes 0 and
1 on the 82575. The PCIe* Card Electromechanical specification does not allow to route a
x2 link to a wider connector. Therefore, a system designer is not allowed to connect a x2
link to lanes 2 and 3 of a PCI e* connector. It is also recommended that when using x2
mode on a NIC, the 82575 is connected to lanes 0 and 1.