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Flow Control — Intel
®
82575EB Gigabit Ethernet Controller
324632-003 Intel
®
82575EB Gigabit Ethernet Controller
Revision: 2.1 Software Developer’s Manual and EEPROM Guide
January 2011 253
Note: “S” is the Start-of-Packet delimiter and “T” is the first part of the End-of-Packet delimiters for 802.3z encapsulation.
Figure 27. 802.3x MAC Control Frame Format
The receiver is enabled to receive flow control frames if flow control is enabled through the RFCE bit in
the Device Control register (CTRL).
Note: Flow control capability must be negotiated between link partners via the Auto-Negotiation
process. The Auto-Negotiation process can modify the value of these bits based on the
resolved capability between the local device and the link partner.
Once the receiver has validated the reception of an XOFF, or PAUSE frame, the 82575 performs the
following:
• Increment the appropriate statistics register(s)
• Set the TXOFF bit in the Device Status Register (STATUS)
• Initialize the pause timer based on the packet’s PAUSE timer field
• Disable packet transmission or schedule the disabling of transmission after the current packet
completes.