Filter
Top Products
Multi-Function Advertisement — Intel
®
82575EB Gigabit Ethernet Controller
324632-003 Intel
®
82575EB Gigabit Ethernet Controller
Revision: 2.1 Software Developer’s Manual and EEPROM Guide
January 2011 283
code of this function changes to other values 10A6h and FF00h, respectively. In addition the function
does not require any memory or I/O space and does not require an interrupt line. Also MSI and MSI-X
capability structure does not appear in this mode. Memory, I/O and master enable bits are read only.
13.5.2 Multi-Function Advertisement
If the LAN 1 port is disabled, the 82575 no longer is a multi-function device. It normally reports a 80h
in the PCI Configuration Header field Header Type, indicating multi-function capability. However, if a
LAN ID is disabled, it reports a 0h in this filed to signify single-function capability.
13.5.3 Legacy Interrupt Use
When both LAN devices are enabled, the 82575 can use interrupt pins INTA# to INTC# for interrupt
reporting. The EEPROM Initialization Control Word 3 (bits 12:11) associated with each LAN device
controls which of these interrupts are used for each LAN device. The specific interrupt pin used is
reported in the PCI Configuration Header Interrupt Pin field associated with each LAN device.
However, if either LAN device is disabled, then INTA# must be used for the remaining LAN device,
regardless of the EEPROM configuration. Under these circumstances, the Interrupt Pin field of the PCI
Header always reports a value of 1h, indicating INTA# usage.
13.5.4 Power Reporting
When both LAN devices are enabled, the PCI Power Management Register Block has the capability of
reporting a Common Power value. The Common Power value is reflected in the data field of the PCI
Power Management registers. The value reported as Common Power is specified via EEPROM, and is
reflected in the data field each time the Data_Select field has a value of 8h (8h = Common Power Value
Select).
When only one LAN is enabled and the 82575 appears as a single-function device, the Common Power
value, if selected, reports 0h (undefined value), as Common Power is undefined for a single-function
device.
13.6 Device Disable
For a LOM design, it might be desirable for the system to provide BIOS-setup capability for selectively
enabling or disabling LOM devices. This allows an end-user more control over system resource-
management; avoid conflicts with add-in NIC solutions, etc. The 82575 provides support for selectively
enabling or disabling it.
Note: If the 82575 is configured to provide a 50 MHz NC-SI clock (via the NC-SI Output Clock
EEPROM bit), then the \Device should not be disabled.
Device Disable is initiated by asserting the asynchronous DEV_OFF_N pin. The DEV_OFF_N pin should
always be connected to enable correct device operation.
The EEPROM Device Disable Power Down En bit enables device disable mode (hardware default is that
the mode is disabled).