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Intel
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82575EB Gigabit Ethernet Controller — Interrupt Cause Read Register - ICR (000C0H; R)
Intel
®
82575EB Gigabit Ethernet Controller 324632-003
Software Developer’s Manual and EEPROM Guide Revision: 2.1
340 January 2011
14.3.34 Interrupt Cause Read Register - ICR (000C0H;
R)
This register contains the interrupt conditions for the 82575 that are not present directly in the EICR.
Each time an ICR interrupt causing event occurs, the corresponding interrupt bit is set in this register.
The EICR.Other bit is reflects the setting of interrupt causes from ICR as masked by the Interrupt Mask
Set/Read register. Each time all un-masked causes in ICR are cleared, the EICR.Other bit is also
cleared.
ICR bits are cleared on register read. Clear-on-read may be enabled/disabled through a general
configuration register bit.
Auto clear is not available for the bits in this register.
In order to prevent unwanted LSC interrupts during initialization, software should disable this interrupt
until the end of initialization.
Field Bit(s)
Initial
Value
Description
TXDW 0 0b Transmit Descriptor Written Back
Set when the 82575 writes back a Tx descriptor to memory.
Reserved 1 0b Reserved
Should be set to 0b for compatibility.
LSC 2 0b Link Status Change
This bit is set each time the link status changes (either from up to down, or from down
to up). This bit is affected by the LINK indication from the PHY (internal PHY mode).
RXSEQ 3 0b Receive Sequence Error
Incoming packets with a bad delimiter sequence set this bit. In other 802.3
implementations, this would be classified as a framing error. A valid sequence consists
of:
idle SOF data pad (opt) EOF fill (opt) idle.
RXDMT0 4 0b Receive Descriptor Minimum Threshold Reached
Indicates that the minimum number of receive descriptors are available and software
should load more receive descriptors.
Reserved 5 0b Reserved
RXO 6 0b Receiver Overrun
Set on receive data FIFO overrun. Could be a result caused by no available receive
buffers or because PCIe* receive bandwidth is inadequate.
RXDW 7 0b Receiver Descriptor Write Back
Set when the 82575 writes back an Rx descriptor to memory.
Reserved 8 0b Reserved
Reads as 0b.
MDAC 9 0b MDIO Access Complete
Set when an MDIO access or an SFP I
2
C transaction completes.
Reserved 10 0b Reserved
GPI_SDP0 11 0b General Purpose Interrupt on SDP0
If GPI interrupt detection is enabled on this pin (via CTRL_EXT), this interrupt cause is
set when the SDP0 is sampled high.
GPI_SDP1 12 0b General Purpose Interrupt on SDP1
If GPI interrupt detection is enabled on this pin (via CTRL_EXT), this interrupt cause is
set when the SDP1 is sampled high.