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Power Management Interconnects — Intel
®
82575EB Gigabit Ethernet Controller
324632-003 Intel
®
82575EB Gigabit Ethernet Controller
Revision: 2.1 Software Developer’s Manual and EEPROM Guide
January 2011 221
7.4.0.3.3 Non-D0a State
The PHY can negotiate to a low speed while in a non-D0a states (Dr, D0u, or D3). This applies only
when the link is required by SMB manageability, APM wake up, or a power management event.
Otherwise, the PHY is disabled during the non-D0 state.
The EEPROM LPLU bit enables reduction in link speed:
• On power-up entry to Dr state, the PHY advertises support for 10 Mb/s only and goes through the
link up process.
• On any entry to a non-D0a state (Dr, D0u, or D3), the PHY advertises support for 10 Mb/s only and
goes through the link up process described as follows.
• While in a non-D0 state, if auto-negotiation is required, the PHY advertises support for
10 Mb/s only and goes through the link up process.
The EEPROM LPLU bit is loaded into the LPLU configuration bit. Software can set or clear this bit at any
time. From that point on, the 82575 acts according to the latest value of the LPLU bit.
Link negotiation begins with the PHY trying to negotiate at 10 Mb/s speed only regardless of user AN
advertisement. If link establishment fails, the PHY tries to negotiate at additional speeds; it enables all
speeds up to the lowest speed supported by the partner. For example, the 82575 advertises 10 Mb only
and the partner supports 1000 Mb only. After the first try fails, the 82575 enables 10/100/1000 Mb/s
and try again. The PHY continues to try and establish a link until it succeeds or until it is instructed
otherwise. In the second step (adjusting to partner speed), the PHY also enables parallel detect, if
needed. Automatic MDI/MDI-X resolution is done during the first auto-negotiation stage.
7.4.0.3.4 Link Energy Detect
The Link Energy Detect MDIO bit is set each time energy is detected on the link. This includes the
period of time during link negotiation and when link is established. This bit should be valid immediately
after a reset of the device or the PHY.
7.4.0.3.5 PHY Power-Down State
Each of the 82575 PHYs enter a power-down state when none of its clients is enabled and therefore, no
need to maintain a link. This can happen in one of several cases as follows:
• PHY power down is enabled through the EEPROM PHY Power Down Enable bit.
• D3/Dr state - each PHY enters a low-power state if the following conditions are met:
— The LAN function associated with this PHY is in a non-D0 state.
— APM Wake on LAN* (WOL) is inactive.
— Manageability does not use this port.
— ACPI PME is disabled for this port.
• SerDes mode - each PHY is disabled when its LAN function is configured in SerDes mode.
• LAN Disable - Each PHY can be disabled if its LAN function’s LAN Disable input indicates that the
relevant function should be disabled. Since the PHY is shared between the LAN function and
manageability, it might not be desired to power down the PHY in LAN Disable. The
PHY_in_LAN_Disable EEPROM bit determines whether the PHY (and MAC) are powered down when
the LAN Disable pin is asserted. The default is not to power down.
A LAN port can also be disabled through EEPROM settings. If the LAN_DIS EEPROM bit is set, the PHY
enters power down. Note, however, that setting the EEPROM LAN_PCI_DIS bit does not bring the PHY
into power down.