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Intel
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82575EB Gigabit Ethernet Controller — MDI Control Register - MDIC (00020h; R/W)
Intel
®
82575EB Gigabit Ethernet Controller 324632-003
Software Developer’s Manual and EEPROM Guide Revision: 2.1
310 January 2011
14.3.7 MDI Control Register - MDIC (00020h; R/W)
Software uses this register to read or write Management Data Interface (MDI) registers in the internal
PHY or an external SGMII PHY.
For an MDI read cycle, the sequence of events is as follows:
• The processor performs a PCIe* write cycle to the MII register with:
— Ready = 0b
— Interrupt Enable set to 1b or 0b
— Opcode = 10b (read)
— PHYADD = PHY address from the MDI register
— REGADD = Register address of the specific register to be accessed (0 through 31)
• The MAC applies the following sequence on the MDIO signal to the PHY:
<PREAMBLE><01><10><PHYADD><REGADD><Z> where Z stands for the MAC tri-stating the
MDIO signal
• The PHY returns the following sequence on the MDIO signal:
<0><DATA><IDLE>
• The MAC discards the leading bit and places the following 16 data bits in the MII register
• The 82575 asserts an interrupt indicating MDI “Done” if the Interrupt Enable bit was set
• The 82575 sets the Ready bit in the MII register indicating the Read is complete.
• The processor might read the data from the MII register and issue a new MDI command
For a MDI write cycle, the sequence of events is as follows:
• Ready = 0b
• Interrupt Enable set to 1b or 0b
• Opcode = 01b (write)
• PHYADD = PHY address from the MDI register
• REGADD = Register address of the specific register to be accessed (0 through 31)
• Data = Specific data for desired control of the PHY
• The MAC applies the following sequence on the MDIO signal to the PHY:
<PREAMBLE><01><01><PHYADD><REGADD><10><DATA><IDLE>
• The 82575 asserts an interrupt indicating MDI “Done” if the Interrupt Enable bit was set
• The 82575 sets the Ready bit in the MII register to indicate that the write operation completed
• The CPU might issue a new MDI command
Note: An MDI read or write might take as long as 64 s from the processor write to the Ready bit
assertion.
If an invalid opcode is written by software, the MAC does not execute any accesses to the PHY registers.
If the PHY does not generate a 0b as the second bit of the turn-around cycle for reads, the MAC aborts
the access, sets the E (error) bit, writes FFFFh to the data field to indicate an error condition, and sets
the Ready bit.