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®
82575EB Gigabit Ethernet Controller
324632-003 Intel
®
82575EB Gigabit Ethernet Controller
Revision: 2.1 Software Developer’s Manual and EEPROM Guide
January 2011 17
14.9.57 SerDes/SGMII Code Violation Packet Count - SCVPC (04228h; R/WS) .......................................432
14.10 Diagnostics Registers ............................................................................................................... 432
14.10.1 Receive Data FIFO Head Register - RDFH (02410h; RO) ..........................................................432
14.10.2 Receive Data FIFO Tail Register - RDFT (02418h; RO).............................................................432
14.10.3 Receive Data FIFO Head Saved Register - RDFHS (02420h; RO) ...............................................433
14.10.4 Receive Data FIFO Tail Saved Register - RDFTS (02428h; RO)..................................................433
14.10.5 Receive Data FIFO Packet Count - RDFPCQ (02430h + 4 *n [n=0..3]; RO).................................433
14.10.6 PB Descriptor Read Pointers - PBDESCRP (02454h; RO) ..........................................................434
14.10.7 Packet Buffer Diagnostic - PBDIAG (02458h; R/W)..................................................................434
14.10.8 Transmit Data FIFO Head Register - TDFH (03410h; RO) .........................................................434
14.10.9 Transmit Data FIFO Tail Register - TDFT (03418h; R/WS)........................................................435
14.10.10 Transmit Data FIFO Head Saved Register - TDFHS (03420h; R/WS)..........................................435
14.10.11 Transmit Data FIFO Tail Saved Register - TDFTS (03428h; R/WS).............................................435
14.10.12 Transmit Data FIFO Packet Count - TDFPC (03430h; RO).........................................................436
14.10.13 Packet Buffer ECC Error Inject - PBEEI (03438h; RO)..............................................................436
14.10.14 Tx Descriptor Handler ECC Error Inject - TDHEEI (035F8h; R/W) ..............................................437
14.10.15 Rx Descriptor Handler ECC Error Inject - RDHEEI (025F8h; R/W)..............................................437
14.10.16 Packet Buffer Memory - PBM (10000h - 10FFCh; R/W) ............................................................438
14.10.17 Packet Buffer Memory Page NPBMPN Register Bit Description ...................................................438
14.10.18 Rx Descriptor Handler Memory Page Number - RDHMP (025FCh; R/W) ......................................438
14.10.19 Tx Descriptor Handler Memory Page Number - TDHMP (035FCh; R/W) ......................................439
14.10.20 Packet Buffer ECC Status - PBECCSTS (0245Ch; R/W).............................................................440
14.10.21 Rx Descriptor Handler ECC Status - RDHESTS (02468h; R/W) ..................................................440
14.10.22 Tx Descriptor Handler ECC Status - TDHESTS (0246Ch; R/W) ..................................................441
14.11 Packet Generator Registers....................................................................................................... 441
14.11.1 Packet Generator Destination Address Low - PGDAL (04280h; R/W)..........................................441
14.11.2 Packet Generator Destination Address High - PGDAH (04284h; R/W) ........................................441
14.11.3 Packet Generator Source Address Low - PGSAL (04288h; R/W) ................................................442
14.11.4 Packet Generator Source Address High - PGSAH (0428Ch; R/W)...............................................442
14.11.5 Packet Generator Inter Packet Gap - PGIPG (04290h; R/W) .....................................................442
14.11.6 Packet Generator Packet Length - PGPL (04294h; R/W)...........................................................443
14.11.7 Packet Generator Number of Packets - PGNP (04298h; R/W)....................................................443
14.11.8 Packet Generator StaPGSTS Bit Description ...........................................................................444
14.11.9 Packet Generator ContPGCTL Bit Description..........................................................................444
14.12 MSI-X Registers ...................................................................................................................... 445
14.12.1 MSI-X Table Entry Lower Address - MSIXTADD (00000h - 00090h; R/W) ...................................446
14.12.2 MSI-X Table Entry Upper Address - MSIXTUADD (BAR3: 0004h + n*10h [n=0..9]; RW) ..............446
14.12.3 MSI-X Table Entry Message - MSIXTMSG (BAR3: 0008h + n*10h [n=0..9]; RW) ........................446
14.12.4 MSI-X Table Entry Vector Control - MSIXVCTRL (BAR3: 000Ch + n*10h [n=0..9]; RW) ...............446
14.12.5 MSI-X Pending Bit Array - MSIXPBA Bit Description.................................................................447
15.0 Diagnostics and Testability ................................................................................................... 449
15.1 Diagnostics............................................................................................................................. 449
15.1.1 FIFO Pointer Accessibility ....................................................................................................449
15.1.2 FIFO Data Accessibility........................................................................................................449
15.1.3 Loopback Operations ..........................................................................................................449
15.2 Testability .............................................................................................................................. 450
15.2.1 EXTEST Instruction.............................................................................................................450
15.2.2 SAMPLE/PRELOAD Instruction ..............................................................................................450
15.2.3 IDCODE Instruction ............................................................................................................450
15.2.4 BYPASS Instruction ............................................................................................................451
16.0 Statistics .............................................................................................................................. 453
16.1 IEEE 802.3 Clause 30 Management............................................................................................ 453
16.2 OID_GEN_STATISTICS............................................................................................................. 454
16.3 RMON .................................................................................................................................... 455
16.4 Linux net_device_stats............................................................................................................. 455