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Intel
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82575EB Gigabit Ethernet Controller — I/O-Mapped Internal Register, Internal Memory,
and Flash
Intel
®
82575EB Gigabit Ethernet Controller 324632-003
Software Developer’s Manual and EEPROM Guide Revision: 2.1
290 January 2011
14.1.1.4 Memory-Mapped Access to Expansion ROM
The external Flash can also be accessed as a memory-mapped expansion ROM. Accesses to offsets
starting from the Expansion ROM Base Address (see Section 6.6.4) reference the Flash provided that
access is enabled through the EEPROM Initialization Control Word, and if the Expansion ROM Base
Address register contains a valid (non-zero) base memory address.
14.1.2 I/O-Mapped Internal Register, Internal
Memory, and Flash
To support pre-boot operation (prior to the allocation of physical memory base addresses), all internal
registers, memories, and Flash can be accessed using I/O operations. I/O accesses are supported only
if an I/O Base Address is allocated and mapped (BAR2 Section 6.6.4), the BAR contains a valid (non-
zero value), and I/O address decoding is enabled in the PCIe* configuration.
When an I/O BAR is mapped, the I/O address range allocated opens a 32-byte window in the system I/
O address map. Within this window, two I/O addressable registers are implemented: IOADDR and
IODATA. The IOADDR register is used to specify a reference to an internal register, memory, or Flash,
and then the IODATA register is used as a window to the register, memory or Flash address specified by
IOADDR:
14.1.2.1 IOADDR
The IOADDR register must always be written as a DWORD access. Writes that are less than 32 bits are
ignored. Reads of any size return a DWORD of data. However, the chipset or processor can only return
a subset of that DWORD.
For software programmers, the IN and OUT instructions must be used to cause I/O cycles to be used on
the PCIe* bus. Since writes must be to a 32-bit quantity, the source register of the OUT instruction
must be EAX (the only 32-bit register supported by the OUT command). For reads, the IN instruction
can have any size target register, but it is recommended that the 32-bit EAX register be used.
Since only a particular range is addressable, the upper bits of this register are hard coded to 0b. Bits 31
through 20 are not write-able and always read back as 0b.
At hardware reset (Internal_Power_On_Reset) or PCI Reset, this register value resets to 00h. Once
written, the value is retained until the next write or reset.
Offset Abbreviation Name RW Size
00h IOADDR Internal Register, Internal Memory, or Flash Location Address
00000h - 1FFFFh — Internal Registers and Memories
20000h - 7FFFFh — Undefined
80000h - 87FFFFh — Flash
RW 4 bytes
04h IODATA Data field for reads or writes to the Internal Register Internal
Memory, or Flash location as identified by the current value in
IOADDR. All 32 bits of this register are read/write-able.
RW 4 bytes
08h - 1Fh Reserved Reserved. RO 4 bytes