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Intel
®
82575EB Gigabit Ethernet Controller — Performance Monitoring
Intel
®
82575EB Gigabit Ethernet Controller 324632-003
Software Developer’s Manual and EEPROM Guide Revision: 2.1
188 January 2011
6.6.1.5 Reset
The PCIe* Physical layer can supply a core reset to the 82575. The reset can be caused by the
following:
1. Upstream move to Hot reset - Inband Mechanism (LTSSM).
2. Recovery failure (LTSSM returns to detect)
3. Upstream component move to disable.
6.6.1.6 Scrambler Disable
The Scrambler/de-scrambler functionality in the 82575 can be eliminated by these mechanisms:
1. Upstream according to the PCIe* specification.
2. EEPROM bit.
6.6.2 Performance Monitoring
The 82575 incorporates PCIe* performance monitoring counters to provide common capabilities for
evaluate performance. It implements four 32-bit counters to correlate between concurrent
measurements of events as well as the sample delay and interval timers. The four 32-bit counters can
also operate in a two 64-bit mode to count long intervals or payloads.
The list of events supported by the 82575 and the counters control bits are described in the memory
register map.
6.6.3 Configuration Registers
6.6.3.1 PCI Compatibility
PCIe* is completely compatible with existing deployed PCI software. To achieve this, PCIe* hardware
implementations conform to the following requirements:
• All devices must be supported by deployed PCI software and must be enumerable as part of a tree
through PCI device enumeration mechanisms.
• Devices must not require any resources such as address decode ranges and interrupts beyond
those claimed by PCI resources for operation of software compatible and software transparent
features with respect to existing deployed PCI software.
• Devices in their default operating state must confirm to PCI ordering and cache coherency rules
from a software viewpoint.
• PCIe* devices must conform to PCI power management specifications and must not require any
register programming for PCI compatible power management beyond those available through PCI
power management capability registers. Power management is expected to conform to a standard
PCI power management by existing PCI bus drivers.
PCIe* devices implement all registers required by the PCI Specification as well as the power
management registers and capability pointers specified by the PCI power management specification. In
addition, PCIe* defines a PCIe* capability pointer to indicate support for PCIe* extensions and
associated capabilities.