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PHY Behavior During a Manageability Session: — Intel
®
82575EB Gigabit Ethernet Controller
324632-003 Intel
®
82575EB Gigabit Ethernet Controller
Revision: 2.1 Software Developer’s Manual and EEPROM Guide
January 2011 41
b. IP Address Valid.
c. IPv4 Address Table
d. IPv6 Address Table
e. Flexible Filter Length Table
f. Flexible Filter Mask Table
13. The Other Configuration Registers includes:
— General Registers
— Interrupt Registers
— Receive Registers
— Transmit Registers
— Statistics Registers
— Diagnostic Registers
Of these registers, MTA[n], VFTA[n], WUPM[n], FFMT[n], FFVT[n], TDBAH/TDBAL, and RDBAH/RDVAL
registers have no default value. If the functions associated with the registers are enabled they must be
programmed by software. Once programmed, their value is preserved through all resets as long as
power is applied to the 82575.
Note: In situations where the 82575 is reset using the software reset CTRL.RST, the TX data lines
are forced to all zeros. This causes a substantial number of symbol errors to be detected by
the link partner.
3.8.1 PHY Behavior During a Manageability Session:
During some manageability sessions (for example a IDER or SOL session as initiated by an external
BMC), the platform is reset so that it boots from a remote media. This reset must not cause the
Ethernet link to drop since the manageability session will be lost. Also, the Ethernet link should be kept
on continuously during the session for the same reasons. The 82575 limits the cases in which the
internal PHY would restart the link, by masking two types of events from the internal PHY:
• PE_RST_N and PCIe* resets (in-band and link drop) do not reset the PHY during such a
manageability session
• The PHY does not change link speed as a result of a change in power management state to avoid
link loss. For example, the transition to D3hot state is not propagated to the PHY.
— Note that if main power is removed, the PHY is allowed to react to the change in power state
(the PHY might respond in link speed change). The motivation for this exception is to reduce
power when operating on auxiliary power by reducing link speed.
The capability described in this section is disabled by default on Internal_Power_On_Reset. The
Keep_PHY_Link_Up_En bit in the EEPROM must be set to 1b to enable it. Once enabled, the feature is
enabled until the next Internal_Power_On_Reset (the 82575 does not revert to the hardware default
value on PE_RST_N, PCIe* reset, or any other reset but Internal_Power_On_Reset).
When the Keep_PHY_Link_Up bit (veto bit) in the MANC register is set, the following behaviors are
disabled:
• The PHY is not reset on PE_RST_N and PCIe* resets (in-band and link drop). Other reset events are
not affected: Internal_Power_On_Reset, Device Disable, Force TCO, and PHY reset by software.
• The PHY does not change its power state. As a result link speed does not change.
• The 82575 does not initiate configuration of the PHY to avoid losing link.