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Intel
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82575EB Gigabit Ethernet Controller — Interrupt Acknowledge Auto Mask Register - IAM
(000E0h; R/W)
Intel
®
82575EB Gigabit Ethernet Controller 324632-003
Software Developer’s Manual and EEPROM Guide Revision: 2.1
344 January 2011
On interrupt handling, the software device driver should set all the bits in this register related to the
current interrupt request even though the interrupt was triggered by part of the causes that were
allocated to this vector.
14.3.38 Interrupt Acknowledge Auto Mask Register -
IAM (000E0h; R/W)
Field Bit(s)
Initial
Value
Description
TXDW 0 0b Clears the Transmit Descriptor Written Back Interrupt.
Reserved 1 - Reserved
LSC 2 0b Clears the Link Status Change Interrupt.
RXSEQ 3 0b Clears the Receive Sequence Error Interrupt.
RXDMT0 4 0b Clears the Receive Descriptor Minimum Threshold Hit Interrupt.
Reserved 5 0b Reserved.
RXO 6 0b Clears the Receiver Overrun Interrupt. Sets on Receive Data FIFO Overrun.
RXDW 7 0b Receiver Descriptor Write Back
Set when the 82575 writes back an Rx descriptor to memory.
Reserved 8 0b Reserved
Reads as 0b.
MDAC 9 0b Clears the MDIO/SFP Access Complete Interrupt.
RXCFG 10 0b Clears the Receiving /C/ Ordered Sets Interrupt.
GPI_SDP0 11 0b Clears the General Purpose Interrupt, related to SDP0 pin.
GPI_SDP1 12 0b Clears the General Purpose Interrupt, related to SDP1 pin.
GPI_SDP2 13 0b Clears the General Purpose Interrupt, related to SDP2 pin.
GPI_SDP3 14 0b Clears the General Purpose Interrupt, related to SDP3 pin.
Reserved 17:15 0b Reserved.
MNG 18 0b Clears the Management Event Interrupt.
Reserved 19 0b Reserved.
OMED 20 0b Clears the Other Media Energy Detected Interrupt.
Reserved 21 0b Reserved.
RX PBUR 22 0b Clears the Receive Packet Buffer Unrecoverable Error Interrupt.
TX PBUR 23 0b Clears the Transmit Packet Buffer Unrecoverable Error Interrupt.
RX DHER 24 0b Clears the Rx Descriptor Handler Error Interrupt.
TX DHER 25 0b Clears the Tx Descriptor Handler Error Interrupt.
SW WD 26 0b Clears the Software Watchdog Interrupt.
Reserved 27 0b Reserved.
OUTSYNC 28 0b Clears the DMA Tx Out of Sync Interrupt.
Reserved 31:29 0000b Reserved.
Field Bit(s)
Initial
Value
Description
IAM_VALUE 31:0 0b Each time the CTRL_EXT.IAME bit is set, an ICR read or write has the side
effect of writing the contents of this register to the IMC register.