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Intel
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82575EB Gigabit Ethernet Controller — Power States
Intel
®
82575EB Gigabit Ethernet Controller 324632-003
Software Developer’s Manual and EEPROM Guide Revision: 2.1
222 January 2011
7.4.0.3.6 SerDes/SGMII Power-Down State
Each of the 82575’s SerDes enters a power-down state when none of its clients are enabled. This case
does not require a link to be maintained. The following conditions must be met for the SerDes to enter
this power-down state:
• SerDes power down must be enabled through the EEPROM SerDes Low Power Enable bit
• D3/Dr state - each SerDes enters a low-power state if the following conditions are met:
— The LAN function associated with this SerDes is in a non-D0 state.
— APM Wake on LAN* (WOL) is inactive.
— Pass through manageability is disabled.
— ACPI PME is disabled.
• PHY mode - each SerDes is disabled when its LAN function is configured in PHY mode.
• LAN Disable - Each SerDes can be disabled if its LAN function’s LAN Disable input indicates that the
relevant function should be disabled. Since the SerDes is shared between the LAN function and
manageability, it might not be desired to power down the SerDes in LAN Disable. The
PHY_in_LAN_Disable EEPROM bit determines whether the SerDes are powered down when the LAN
Disable pin is asserted. The default is not to power down.
7.4.1 Power States
7.4.1.1 Dr State
Transition to Dr state is initiated as follows:
• On system power up. The Dr state starts with the assertion of the internal power detection circuit
(Internal_Power_On_Reset) and ends with de-asserting PE_RST_N.
• On transition from a D0a state. During operation, the system might assert PE_RST_N at any time.
In an ACPI system, a system transition to the G2/S5 state causes a transition from D0a to Dr.
• On transition from a D3 state. The system transitions the 82575 into the Dr state by asserting
PE_RST_N.
Any wake-up filter settings that were enabled before entering this reset state are maintained.
The system might maintain PE_RST_N assertion for an arbitrary time. The de-assertion (rising edge)
PE_RST_N causes a transition to the D0u state.
While in Dr state, the 82575 might enter one of several modes with different levels of functionality and
power consumption. The lower-power modes are achieved when the 82575 is not required to maintain
any functionality. The Dr Disable mode is described in “Entry to Dr State”.
Note: If the 82575 is configured to provide a 50 MHz NC-SI clock (via the NC-SI Output Clock
EEPROM bit), then the NC-SI clock must be provided in Dr state as well.
7.4.1.1.1 Dr Disable Mode
The 82575 enters a Dr Disable mode on transition to D3cold state when it does not need to maintain
any functionality. The conditions to enter either state are:
• The 82575 (all PCI functions) is in Dr state
• APM WOL is inactive for both LAN functions