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SerDes/CCM/PCIe* CSR - GIOANACTL0 (05B34h; R/W) — Intel
®
82575EB Gigabit Ethernet
Controller
324632-003 Intel
®
82575EB Gigabit Ethernet Controller
Revision: 2.1 Software Developer’s Manual and EEPROM Guide
January 2011 409
14.8.12 SerDes/CCM/PCIe* CSR - GIOANACTL0
(05B34h; R/W)
Firmware uses this register for analog circuit configuration.
14.8.13 SerDes/CCM/PCIe* CSR - GIOANACTL1
(05B38h; R/W)
Firmware uses this register for analog circuit configuration.
14.8.14 GIOANACTL2 (05B3Ch; R/W)
Firmware uses this register for analog circuit configuration.
Func0 Aux_En 3 0b Function 0 Auxiliary (AUX) Power PM Enable bit shadow from the configuration space.
LAN0 Valid 2 0b LAN 0 Enable
When set to 0b, it indicates that the LAN 0 function is disabled. When the function is
enabled, the bit is set to 1b.
The LAN 0 enable is set by the LAN 0 Enable / TEST_POINT[2] strapping pin.
Func0 Power
State
1:0 00b Power state indication of Function 0
00b -> DR
01b -> D0u
10b -> D0a
11b -> D3
Field Bit(s)
Initial
Value
Description
Done Indication 31 1b When a write operation completes this bit is set to 1b indicating that new data
can be written. This bit is over written to 0b by new data.
Reserved 30:16 0b Reserved.
Address 15:8 0b Address to SerDes.
Data 7:0 0b Data to SerDes.
Field Bit(s)
Initial
Value
Description
Done Indication 31 1b When a write operation completes this bit is set to 1b indicating that new data
can be written. This bit is over written to 0b by new data.
Reserved 30:16 0b Reserved.
Address 15:8 0b Address to SerDes.
Data 7:0 0b Data to SerDes.
Field Bit(s)
Initial
Value
Description
Done Indication 31 1b When a write operation completes this bit is set to 1b indicating that new data
can be written. This bit is over written to 0b by new data.