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Intel
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82575EB Gigabit Ethernet Controller — Reset Operation
Intel
®
82575EB Gigabit Ethernet Controller 324632-003
Software Developer’s Manual and EEPROM Guide Revision: 2.1
38 January 2011
D3hot to D0 Transition:
This is also known as ACPI Reset. The 82575 generates an internal reset on the transition from D3hot
power state to D0 (caused after configuration writes from D3 to D0 power state). Note that this reset is
per function and resets only the function that transitioned from D3hot to D0.
Software Reset:
Software can reset the 82575 by writing the Device Reset bit of the Device Control register (CTRL.RST).
The 82575 re-reads the per-function EEPROM fields after a software reset. Bits that are normally read
from the EEPROM are reset to their default hardware values. Note that this reset is per function and
resets only the function that received the software reset. PCI Configuration space (configuration and
mapping) of the 82575 is unaffected. Prior to issuing a software reset the software device driver needs
to operate the master disable algorithm.
Force TCO:
This reset is generated when manageability logic is enabled. It is only be generated if the Reset on
Force TCO bit of the EEPROM's Management Control word is 1b. In pass through mode it is generated
when receiving a ForceTCO SMB command with bit 1 or bit 7 set. EEPROM Reset:
Writing a 1b to the EEPROM Reset bit of the Extended Device Control Register (CTRL_EXT.EE_RST)
causes the 82575 to re-read the per-function configuration from the EEPROM, setting the appropriate
bits in the registers loaded by the EEPROM.
PHY Reset:
Software can write a 1b to the PHY Reset bit of the Device Control Register (CTRL.PHY_RST) to reset
the internal PHY. The firmware must configure the PHY following a PHY Reset.
The procedure for resetting the PHY by software is as follows:
1. Take PHY ownership using the software semaphore (SWSM.SWESMBI - 05B50h, bit 1 and
SY_FW_SYNC.SW_PHY_SM0/1 - 05B5Ch, bit 1/2).
2. Drive PHY reset.
3. Wait 10 ms
4. Release PHY reset in the CTRL register.
5. Release PHY and EEPROM ownership using the software semaphore (SWSM.SWESMBI - 05B50h, bit
1 and SY_FW_SYNC. SW_PHY_SM0/1, SY_FW_SYNC. SW_EEP_SM - 05B5Ch, bit 1/2/0).
6. Wait for the CFG_DONE (EEMNGCTL.CFG_DONE - 1010h, bit 18).
7. Start configuring the PHY.
Note: Refer to Section 14.0 for a description of software/firmware semaphore usage.
The resets affect the registers and logic listed in Table 3.