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Initialize the Receive Control Register — Intel
®
82575EB Gigabit Ethernet Controller
324632-003 Intel
®
82575EB Gigabit Ethernet Controller
Revision: 2.1 Software Developer’s Manual and EEPROM Guide
January 2011 31
• Enable the queue by setting RXDCTL.ENABLE. In the case of queue zero, the enable bit is set by
default, as such, the ring parameters should be set before RCTL.RXEN is set.
• Program the direction of packets to this queue according to the mode select in MRQC. Packets
directed to a disabled queue are dropped.
3.5.1 Initialize the Receive Control Register
To properly receive packets, the receiver should be enabled by setting RCTL.RXEN. This should be done
only after all other setup is accomplished. If software uses the Receive Descriptor Minimum Threshold
Interrupt, that value should be set.
Note: The Receive Descriptor Tail register of the queue (RDT[n]) should not be bumped until the
queue is enabled. This register must also be written after the queue is enabled and the
receiver is enabled.
3.5.2 Dynamic Queue Enabling and Disabling
Receive queues can be dynamically enabled or disabled provided the following procedure is followed:
Enabling:
• Follow the per queue initialization previously described.
• If there are still packets in the packet buffer directed to this queue according to previous settings,
they are received after the queue is re-enabled. The software device driver might check if old
packets are still in the internal packet buffer by reading the RDFPCQ# register of the queue.
Disabling:
• Disable the direction of packets to this queue.
• Disable the queue by clearing RXDCTL.ENABLE. The 82575 immediately stops to fetch and write
back descriptors from this queue. The 82575 eventually completes the storage of one buffer
allocated to this queue. Any further packet directed to this queue is dropped. If the currently
processed packet is spread over more than one buffer, all subsequent buffers are not written.
• The 82575 clears RXDCTL.ENABLE only after all pending memory accesses to the descriptor ring or
to the buffers are done. The software device drive should poll this bit before releasing the memory
allocated to this queue.
The Rx path can be disabled only after all Rx queues are disabled.
3.6 Transmit Initialization
Program the TCTL register according to the required MAC behavior.
If work in half duplex mode is expected, program the TCTL_EXT.COLD field. For internal PHY mode, the
default value is 41h. For SGMII mode, a value reflecting the 82575 and the PHY SGMII delays should be
used. A suggested value for a typical PHY is 46h for 10 Mb/s and 4Ch for 100 Mb/s.
The following should be done once per transmit queue:
• Allocate a region of memory for the transmit descriptor list.
• Program the descriptor base address with the address of the region.