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Intel
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82575EB Gigabit Ethernet Controller — BIOS Handling of Device Disable
Intel
®
82575EB Gigabit Ethernet Controller 324632-003
Software Developer’s Manual and EEPROM Guide Revision: 2.1
284 January 2011
While in device disable mode, the PCIe* link is in L3 state. The PHY is in power down mode. Output
buffers are tri-stated.
Asserting or deasserting the PCIe* PE_RST_N does not have any effect while the 82575 is in device
disable mode (for example, the 82575 stays in the respective mode as long as DEV_OFF_N is asserted).
However, the 82575 might momentarily exit the device disable mode from the time PCIe* PE_RST_N is
de-asserted again and until the EEPROM is read.
During power-up, the DEV_OFF_N pin is ignored until the EEPROM is read. From that point, the 82575
might enter Device Disable if DEV_OFF_N is asserted.
Deasserting the DEV_OFF_N pin causes a fundamental reset to the 82575.
Note: The DEV_OFF_N pin should maintain its state during system reset and system sleep states.
It should also insure the proper default value on system power-up. For example, a designer
could use a GPIO pin that defaults to 1b (enable) and is on system suspend power (it
maintains state in S0-S5 ACPI states).
13.6.1 BIOS Handling of Device Disable
1. Assume that following a power up sequence, the DEV_OFF_N signals is driven high (else it is
already disabled).
2. The PCIe* is established following the GIO_PWR_GOOD
3. BIOS recognizes that the entire 82575 should be disabled.
4. The BIOS drives the DEV_OFF_N signal to the low level.
5. As a result, the 82575 samples the DEV_OFF_N signals and enters device disable mode.
6. The BIOS could put the Link in the Electrical IDLE state (at the other end of the PCIe* link) by
clearing the LINK Disable bit in the Link Control Register.
7. Proceed with normal operation
8. Re-enable could be done by driving the DEV_OFF_N signal high, followed later by bus enumeration.
13.7 Copper/Fiber Switch
The 82575 component provides significant amount of flexibility in pairing a LAN device with a particular
type of media (for example, copper or fiber-optic) as well as the specific transceiver/interface used to
communicate with the media. Each MAC, representing a distinct LAN device, can be coupled with an
internal copper PHY (the default) or SerDes interface independently. The link configuration specified for
each LAN device can be specified in the LINK_MODE field of the Extended Device Control Register
(CTRL_EXT) and initialized from the EEPROM Initialization Control Word 3 associated with each LAN
device.
In some applications, software might need to be aware of the presence of a link on the connection not
currently active. In order to supply such an indication, any of the 82575 ports can set the
AUTOSENSE_EN bit in the CONNSW register (address 00034h) in order to enable sensing of the non
active connection activity. When in SerDes detect mode, software should define which indication is used
to detect the energy change in SerDes/SGMII mode. It can be either the external signal detect pin or
the internal signal detect. This is done using the CONNSW.ENRGSRC bit.